added buffering to EFO signals

dataflow_neuro/chips.act

@@ -80,7 +80,9 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
 
     power supply;
-    bool? reset_B, reset_reg_B){
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    bool! reset_nrn_hs_BO[N_NRN_X], reset_syn_hs_BO[N_SYN_X],
+    reset_nrn_stge_BO[N_NRN_X], reset_syn_stge_BO[N_SYN_X]){
 
     bool _reset_BX;
     BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
@@ -263,30 +265,36 @@ defproc texel_core (avMx1of2<N_IN> in, out;
 
     )
 
-    // Create NON buffered signals from register to nrns.
+    // Create buffered signals from register to nrns.
+    sigbuf_boolarray<N_FLAGS_PER_NRN, 31> sb_nrn_EFO(.out = nrn_flags_EFO, .supply = supply);
     (i:N_FLAGS_PER_NRN:
-        nrn_flags_EFO[i] = register.data[5].d[i].t;
+        sb_nrn_EFO.in[i] = register.data[5].d[i].t;
     )
 
-    // Create NON buffered signals from register to synapses.
+    // Create buffered signals from register to synapses.
     // Includes safety on the first 3 flags with dev mon.
+    sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
     (i:3..N_FLAGS_PER_SYN-1:
-        syn_flags_EFO[i] = register.data[4].d[i].t;
+        sb_syn_EFO.in[i] = register.data[4].d[i].t;
     )  
     AND2_X1 syn_flags_dev_safety[3];
-    BUF_X4 syn_flags_dev_safety_sb[3];
     (i:0..2:
         syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
         syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
-        syn_flags_dev_safety_sb[i].a = syn_flags_dev_safety[i].y;
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y
-        syn_flags_dev_safety_sb[i].y = syn_flags_EFO[i];
 
         syn_flags_dev_safety[i].vdd = supply.vdd;
         syn_flags_dev_safety[i].vss = supply.vss;
-        syn_flags_dev_safety_sb[i].vdd = supply.vdd;
-        syn_flags_dev_safety_sb[i].vss = supply.vss;
     )
 
+    // Create non-buffered reset signals for the neuron/syn handshakes
+    // Since sigs are buffered before each neuron.
+    sigbuf<N_SYN_X> rsb_syn_hs(.in = _reset_BX, .out = reset_syn_hs_BO, .supply = supply);
+    sigbuf<N_NRN_X> rsb_nrn_hs(.in = _reset_BX, .out = reset_nrn_hs_BO, .supply = supply);
+    sigbuf<N_SYN_X> rsb_syn_storage(.in = reset_syn_stge_BI, .out = reset_syn_stge_BO, .supply = supply);
+    INV_X1 nrn_reset_stge_inv(.a = register.data[0].d[6].t, .vdd = supply.vdd, .vss = supply.vss);
+    sigbuf<N_NRN_X> rsb_nrn_storage(.in = nrn_reset_stge_inv.y, .out = reset_nrn_stge_BO, .supply = supply);
+
 }
 
 
@@ -390,9 +398,6 @@ REG_NCA, REG_NCW, REG_M>
 defproc texel_dualcore (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
-
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
     
     bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
     bool? c1_dec_ackB[N_SYN_X];
@@ -409,9 +414,6 @@ defproc texel_dualcore (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c2_reg_data[REG_M];
 
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-    
     bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
     bool? c2_dec_ackB[N_SYN_X];
     a1of1 c2_syn_pu[N_SYN_X];
@@ -428,7 +430,14 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
     power supply;
-    bool? reset_B, reset_reg_B){
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+    
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X]
+    ){
 
     // Reset buffers
     bool _reset_BX;
@@ -474,7 +483,10 @@ defproc texel_dualcore (bd<N_IN> in, out;
             .syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
             .syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
 
-            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c1_reset_syn_hs_BO, .reset_syn_stge_BO = c1_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .reset_nrn_stge_BO = c1_reset_nrn_stge_BO,
+
             .supply = supply
             );
 
@@ -499,7 +511,10 @@ defproc texel_dualcore (bd<N_IN> in, out;
             .syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
             .syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
 
-            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
+            .reset_B = _reset_BX, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+            .reset_syn_hs_BO = c2_reset_syn_hs_BO, .reset_syn_stge_BO = c2_reset_syn_stge_BO,
+            .reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .reset_nrn_stge_BO = c2_reset_nrn_stge_BO,
+            
             .supply = supply
             );
 

test/unit_tests/texel_dualcore/test.act

@@ -63,10 +63,10 @@ pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
 pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
 
 pint N_MON_AMZO_PER_SYN = 5;
-pint N_MON_AMZO_PER_NRN = 7;
+pint N_MON_AMZO_PER_NRN = 3;
 
-pint N_FLAGS_PER_SYN = 4; // Syn: Must be at least 3 (since those ones have special safety)
+pint N_FLAGS_PER_SYN = 5; // Syn: Must be at least 3 (since those ones have special safety)
-pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
+pint N_FLAGS_PER_NRN = 3; // and leq than the number of bits in a reg, since have presumed only needs one.
 
 pint N_BUFFERS = 3;