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fa5f83f061
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eda9e2a98b
@ -414,10 +414,14 @@ defproc registerA_w_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M];
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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// Input valid tree
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// Note that I may need to check the validity of other downstream stuff,
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// to be ultra careful about delays.
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// e.g. TODO add validity checking on the selector signals.
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vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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@ -433,10 +437,10 @@ A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = in.a,
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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A_2C_B_X1 write_selectors[M];
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AND2_X1 write_selectors[M];
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(i:M:
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write_selectors[i].c1 = _w;
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write_selectors[i].c2 = decoder.out[i];
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write_selectors[i].a = _w;
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write_selectors[i].b = decoder.out[i];
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write_selectors[i].vdd = supply.vdd;
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write_selectors[i].vss = supply.vss;
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)
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@ -468,153 +472,6 @@ TIELO_X1 tielow_writebit_f[M];
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}
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/**
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* Array of registers made out of A-cells
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* params:
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* NcW: number of bits in Words to be stored in buffers
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* NcA: number of bits in Address
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* M: number of registers. M = 2^Nc_addr would be a natural choice.
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* Input packets should be
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* [-addr-][-word-][r/w]
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*/
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export template<pint NcA, NcW, M>
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defproc registerA_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
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bool? reset_B; power supply) {
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// BIG TODO
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// I HAVE NOT BOTHERED WITH ANY SIGNAL BUFFERING IN HERE YET
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// Input valid tree
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vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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decoder.in.d[i] = in.d.d[i];
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)
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// OrTree over acks from all registers
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ortree<M> ack_ortree(.supply = supply);
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bool _write_ack;
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// C element handling in ack
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A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
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.vss = supply.vss, .vdd = supply.vdd);
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// Bit to join the acks either from read or write
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bool _read_ack;
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_read_ack = out.a;
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OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack, .y = in.a,
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.vdd = supply.vdd, .vss = supply.vss);
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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A_2C_B_X1 write_selectors[M];
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(i:M:
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write_selectors[i].c1 = _w;
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write_selectors[i].c2 = decoder.out[i];
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write_selectors[i].vdd = supply.vdd;
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write_selectors[i].vss = supply.vss;
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)
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// Registers
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registerA<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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(j:NcW:
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registers[i].in.d.d[j] = in.d.d[j + NcA];
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)
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// Connect the (selected) write bit
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registers[i].in.d.d[NcW].t = write_selectors[i].y;
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tielow_writebit_f[i].vdd = supply.vdd;
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tielow_writebit_f[i].vss = supply.vss;
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registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// Connect to ack ortree
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registers[i].in.a = ack_ortree.in[i];
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// Connect outputs
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data[i] = registers[i].out;
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registers[i].supply = supply;
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registers[i].reset_B = reset_B;
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)
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// Read bit selector
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bool _r = in.d.d[NcA+NcW].f;
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A_2C_B_X1 read_selectors[M];
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(i:M:
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read_selectors[i].c1 = _r;
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read_selectors[i].c2 = decoder.out[i];
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read_selectors[i].vdd = supply.vdd;
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read_selectors[i].vss = supply.vss;
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)
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// OrTrees for each output word bit on read
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ortree<M> out_ortrees_t[NcW];
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ortree<M> out_ortrees_f[NcW];
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(i:NcW:
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out_ortrees_t[i].out = out.d.d[i+NcA].t;
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out_ortrees_f[i].out = out.d.d[i+NcA].f;
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out_ortrees_t[i].supply = supply;
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out_ortrees_f[i].supply = supply;
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)
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// ANDs over each reg's data
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// and whether it is selected for read.
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AND2_X1 and_reads_t[NcW * M];
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AND2_X1 and_reads_f[NcW * M];
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pint index;
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(i:NcW:
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(j:M:
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index = i + j*NcW;
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and_reads_t[index].a = data[j].d[i].t;
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and_reads_t[index].b = read_selectors[j].y;
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and_reads_f[index].a = data[j].d[i].f;
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and_reads_f[index].b = read_selectors[j].y;
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and_reads_t[index].y = out_ortrees_t[i].in[j];
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and_reads_f[index].y = out_ortrees_f[i].in[j];
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and_reads_t[index].vss = supply.vss;
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and_reads_t[index].vdd = supply.vdd;
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and_reads_f[index].vss = supply.vss;
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and_reads_f[index].vdd = supply.vdd;
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)
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)
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// C elements passing address to out on read.
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A_2C_B_X1 addr_read_t[NcA];
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A_2C_B_X1 addr_read_f[NcA];
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(i:NcA:
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addr_read_t[i].c1 = in.d.d[i].t;
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addr_read_f[i].c1 = in.d.d[i].f;
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addr_read_t[i].c2 = _r;
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addr_read_f[i].c2 = _r;
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addr_read_t[i].y = out.d.d[i].t;
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addr_read_f[i].y = out.d.d[i].f;
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addr_read_t[i].vdd = supply.vdd;
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addr_read_t[i].vss = supply.vss;
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addr_read_f[i].vdd = supply.vdd;
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addr_read_f[i].vss = supply.vss;
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)
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}
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File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,55 +0,0 @@
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/registers.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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defproc registerA_wr_array_3x5x8 (avMx1of2<3+5+1> in; Mx1of2<5> data[8]; avMx1of2<8> out){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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// Make a register array with 3 bit address (-> 8 registers),
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// each register holding 5 bits.
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registerA_wr_array<3,5,8> b(.in = in, .data = data, .out = out,
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.reset_B = _reset_B, .supply = supply);
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}
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// fifo_decoder_neurons_encoder_fifo e;
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registerA_wr_array_3x5x8 b;
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@ -1,199 +0,0 @@
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watchall
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set-qdi-channel-neutral "b.in" 9
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set b.out.a 0
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set b.out.v 0
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cycle
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mode run
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg0'"
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set-qdi-channel-valid "b.in" 9 256
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cycle
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assert b.in.a 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Sending packet write 0s to reg0'"
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set-qdi-channel-valid "b.in" 9 256
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cycle
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assert b.in.a 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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assert-var-int "b.data[0]" 5 0
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system "echo '[] Sending packet write 01100=12 to reg0'"
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set-qdi-channel-valid "b.in" 9 352
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cycle
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assert b.in.a 1
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assert b.in.v 1
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assert-var-int "b.data[0]" 5 12
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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assert-var-int "b.data[0]" 5 12
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system "echo '[] Sending packet write 0s to reg1'"
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set-qdi-channel-valid "b.in" 9 257
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cycle
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assert b.in.a 1
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assert b.in.v 1
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assert-var-int "b.data[1]" 5 0
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg2'"
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set-qdi-channel-valid "b.in" 9 258
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cycle
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assert b.in.a 1
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assert b.in.v 1
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assert-var-int "b.data[2]" 5 0
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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assert-var-int "b.data[2]" 5 0
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system "echo '[] Sending packet write 0s to reg3'"
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set-qdi-channel-valid "b.in" 9 259
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cycle
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assert b.in.a 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg4'"
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set-qdi-channel-valid "b.in" 9 260
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cycle
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assert b.in.a 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg5'"
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set-qdi-channel-valid "b.in" 9 261
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cycle
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assert b.in.a 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg6'"
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set-qdi-channel-valid "b.in" 9 262
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cycle
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assert b.in.a 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Sending packet write 0s to reg7'"
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set-qdi-channel-valid "b.in" 9 263
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cycle
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assert b.in.a 1
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assert b.in.v 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert b.in.a 0
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assert b.in.v 0
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assert-var-int "b.data[2]" 5 0
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assert-var-int "b.data[3]" 5 0
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assert-var-int "b.data[4]" 5 0
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assert-var-int "b.data[5]" 5 0
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assert-var-int "b.data[6]" 5 0
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assert-var-int "b.data[7]" 5 0
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system "echo '[] Reading register 0'"
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set-qdi-channel-valid "b.in" 9 0
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cycle
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assert-qdi-channel-valid "b.out" 8 96
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assert b.in.v 1
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assert b.in.a 0
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set b.out.a 1
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set b.out.v 1
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cycle
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assert b.in.a 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert-qdi-channel-neutral "b.out" 8
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set b.out.a 0
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set b.out.v 0
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cycle
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assert b.in.a 0
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assert b.in.v 0
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system "echo '[] Reading register 1'"
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set-qdi-channel-valid "b.in" 9 1
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cycle
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assert-qdi-channel-valid "b.out" 8 1
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assert b.in.v 1
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assert b.in.a 0
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set b.out.a 1
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set b.out.v 1
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cycle
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assert b.in.a 1
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system "echo '[] Removing input'"
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set-qdi-channel-neutral "b.in" 9
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cycle
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assert-qdi-channel-neutral "b.out" 8
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set b.out.a 0
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set b.out.v 0
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cycle
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assert b.in.a 0
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assert b.in.v 0
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