55 lines
1.6 KiB
Verilog
55 lines
1.6 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0ctree_313_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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input Iin5 ;
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input Iin6 ;
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input Iin7 ;
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input Iin8 ;
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input Iin9 ;
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input Iin10 ;
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input Iin11 ;
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input Iin12 ;
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output out;
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// -- signals ---
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wire Itmp20 ;
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wire Itmp17 ;
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wire Iin6 ;
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wire Itmp21 ;
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wire Iin0 ;
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wire Itmp16 ;
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wire Iin5 ;
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wire Iin9 ;
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wire Iin7 ;
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wire Iin12 ;
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wire Iin10 ;
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wire Itmp19 ;
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wire Iin8 ;
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wire Iin2 ;
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wire Iin1 ;
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wire Itmp15 ;
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wire Itmp14 ;
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wire Iin3 ;
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wire out ;
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wire Iin4 ;
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wire Iin11 ;
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wire Itmp18 ;
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wire Itmp13 ;
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// --- instances
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A_2C_B_X1 IC2Els0 (.y(Itmp13 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els1 (.y(Itmp14 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els2 (.y(Itmp15 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els3 (.y(Itmp16 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els4 (.y(Itmp17 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els5 (.y(Itmp19 ), .c1(Itmp13 ), .c2(Itmp14 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els6 (.y(Itmp20 ), .c1(Itmp15 ), .c2(Itmp16 ), .vdd(vdd), .vss(vss));
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A_2C_B_X1 IC2Els7 (.y(Itmp21 ), .c1(Itmp17 ), .c2(Itmp18 ), .vdd(vdd), .vss(vss));
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A_3C_B_X1 IC3Els0 (.y(Itmp18 ), .c1(Iin10 ), .c2(Iin11 ), .c3(Iin12 ), .vdd(vdd), .vss(vss));
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A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp19 ), .c2(Itmp20 ), .c3(Itmp21 ), .vdd(vdd), .vss(vss));
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endmodule |