193 lines
6.8 KiB
Verilog
193 lines
6.8 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_36_760_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , Iin_d5_d0 , Iin_d5_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Iout30 , Iout31 , Iout32 , Iout33 , Iout34 , Iout35 , Iout36 , Iout37 , Iout38 , Iout39 , Iout40 , Iout41 , Iout42 , Iout43 , Iout44 , Iout45 , Iout46 , Iout47 , Iout48 , Iout49 , Iout50 , Iout51 , Iout52 , Iout53 , Iout54 , Iout55 , Iout56 , Iout57 , Iout58 , Iout59 , vdd, vss);
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input vdd;
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input vss;
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input Iin_d0_d0 ;
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input Iin_d0_d1 ;
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input Iin_d1_d0 ;
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input Iin_d1_d1 ;
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input Iin_d2_d0 ;
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input Iin_d2_d1 ;
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input Iin_d3_d0 ;
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input Iin_d3_d1 ;
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input Iin_d4_d0 ;
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input Iin_d4_d1 ;
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input Iin_d5_d0 ;
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input Iin_d5_d1 ;
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input en;
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// -- signals ---
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wire Iin_d1_d0 ;
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wire Iin_d0_d1 ;
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output Iout55 ;
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wire Idecoder_final_refresh_d3_d1 ;
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output Iout29 ;
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wire Idecoder_final_refresh_d0_d0 ;
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output Iout58 ;
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output Iout20 ;
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output Iout15 ;
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output Iout6 ;
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wire Idecoder_final_refresh_d0_d1 ;
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output Iout57 ;
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output Iout51 ;
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output Iout40 ;
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wire Ien_ands_f1_y ;
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output Iout11 ;
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output Iout50 ;
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output Iout47 ;
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output Iout38 ;
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output Iout12 ;
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output Iout5 ;
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output Iout49 ;
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output Iout44 ;
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output Iout31 ;
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output Iout23 ;
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wire Ien_ands_t2_y ;
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wire Idecoder_final_refresh_d1_d0 ;
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output Iout9 ;
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wire Ien_ands_f2_y ;
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wire Idecoder_final_refresh_d5_d0 ;
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output Iout56 ;
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output Iout24 ;
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output Iout2 ;
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output Iout39 ;
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output Iout21 ;
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wire Iin_d4_d1 ;
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wire Isb_en_out0 ;
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wire Idecoder_final_refresh_d4_d0 ;
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output Iout37 ;
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wire Iin_d5_d1 ;
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wire Idecoder_final_refresh_d4_d1 ;
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output Iout27 ;
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output Iout8 ;
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output Iout7 ;
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wire Iin_d0_d0 ;
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wire Idecoder_final_refresh_d1_d1 ;
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output Iout36 ;
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wire Ien_ands_f5_y ;
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wire Iin_d2_d0 ;
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output Iout59 ;
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output Iout43 ;
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output Iout26 ;
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output Iout22 ;
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wire Iin_d1_d1 ;
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output Iout45 ;
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output Iout42 ;
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output Iout4 ;
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wire Idecoder_final_refresh_d5_d1 ;
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output Iout52 ;
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wire Ien_ands_f3_y ;
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output Iout34 ;
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wire Ien_ands_t4_y ;
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wire Ien_ands_t3_y ;
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wire Ien_ands_t0_y ;
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output Iout16 ;
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output Iout25 ;
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output Iout53 ;
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output Iout14 ;
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wire Ien_ands_t1_y ;
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output Iout35 ;
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wire Ien_ands_t5_y ;
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wire Iin_d5_d0 ;
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wire Iin_d3_d0 ;
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output Iout32 ;
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output Iout30 ;
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output Iout17 ;
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wire Idecoder_final_refresh_d2_d1 ;
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output Iout48 ;
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output Iout46 ;
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output Iout13 ;
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wire Iin_d3_d1 ;
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wire en;
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wire Ien_ands_f0_y ;
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wire Iin_d4_d0 ;
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wire Iin_d2_d1 ;
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wire Idecoder_final_refresh_d3_d0 ;
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output Iout10 ;
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wire Ien_ands_f4_y ;
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wire Idecoder_final_refresh_d2_d0 ;
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output Iout54 ;
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output Iout28 ;
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output Iout19 ;
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output Iout0 ;
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output Iout33 ;
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output Iout3 ;
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output Iout41 ;
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output Iout18 ;
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output Iout1 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_36_760_4 Idecoder (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iin_d5_d0 (Ien_ands_f5_y ), .Iin_d5_d1 (Ien_ands_t5_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Iout30 (Iout30 ), .Iout31 (Iout31 ), .Iout32 (Iout32 ), .Iout33 (Iout33 ), .Iout34 (Iout34 ), .Iout35 (Iout35 ), .Iout36 (Iout36 ), .Iout37 (Iout37 ), .Iout38 (Iout38 ), .Iout39 (Iout39 ), .Iout40 (Iout40 ), .Iout41 (Iout41 ), .Iout42 (Iout42 ), .Iout43 (Iout43 ), .Iout44 (Iout44 ), .Iout45 (Iout45 ), .Iout46 (Iout46 ), .Iout47 (Iout47 ), .Iout48 (Iout48 ), .Iout49 (Iout49 ), .Iout50 (Iout50 ), .Iout51 (Iout51 ), .Iout52 (Iout52 ), .Iout53 (Iout53 ), .Iout54 (Iout54 ), .Iout55 (Iout55 ), .Iout56 (Iout56 ), .Iout57 (Iout57 ), .Iout58 (Iout58 ), .Iout59 (Iout59 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .Ifinal_refresh_d5_d0 (Idecoder_final_refresh_d5_d0 ), .Ifinal_refresh_d5_d1 (Idecoder_final_refresh_d5_d1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_312_4 Isb_en (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t0 (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t1 (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t2 (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t3 (.y(Ien_ands_t3_y ), .a(Iin_d3_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t4 (.y(Ien_ands_t4_y ), .a(Iin_d4_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_t5 (.y(Ien_ands_t5_y ), .a(Iin_d5_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f0 (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f1 (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f2 (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f3 (.y(Ien_ands_f3_y ), .a(Iin_d3_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f4 (.y(Ien_ands_f4_y ), .a(Iin_d4_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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AND2_X1 Ien_ands_f5 (.y(Ien_ands_f5_y ), .a(Iin_d5_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
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endmodule |