373 lines
19 KiB
Verilog
373 lines
19 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0encoder2d__simple_34_73_715_76_72_4(Iinx0_d_d0 , Iinx0_a , Iinx1_d_d0 , Iinx1_a , Iinx2_d_d0 , Iinx2_a , Iinx3_d_d0 , Iinx3_a , Iinx4_d_d0 , Iinx4_a , Iinx5_d_d0 , Iinx5_a , Iinx6_d_d0 , Iinx6_a , Iinx7_d_d0 , Iinx7_a , Iinx8_d_d0 , Iinx8_a , Iinx9_d_d0 , Iinx9_a , Iinx10_d_d0 , Iinx10_a , Iinx11_d_d0 , Iinx11_a , Iinx12_d_d0 , Iinx12_a , Iinx13_d_d0 , Iinx13_a , Iinx14_d_d0 , Iinx14_a , Iiny0_d_d0 , Iiny0_a , Iiny1_d_d0 , Iiny1_a , Iiny2_d_d0 , Iiny2_a , Iiny3_d_d0 , Iiny3_a , Iiny4_d_d0 , Iiny4_a , Iiny5_d_d0 , Iiny5_a , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_a , Iout_v , Ito_pd_x0_d_d0 , Ito_pd_x0_a , Ito_pd_x1_d_d0 , Ito_pd_x1_a , Ito_pd_x2_d_d0 , Ito_pd_x2_a , Ito_pd_x3_d_d0 , Ito_pd_x3_a , Ito_pd_x4_d_d0 , Ito_pd_x4_a , Ito_pd_x5_d_d0 , Ito_pd_x5_a , Ito_pd_x6_d_d0 , Ito_pd_x6_a , Ito_pd_x7_d_d0 , Ito_pd_x7_a , Ito_pd_x8_d_d0 , Ito_pd_x8_a , Ito_pd_x9_d_d0 , Ito_pd_x9_a , Ito_pd_x10_d_d0 , Ito_pd_x10_a , Ito_pd_x11_d_d0 , Ito_pd_x11_a , Ito_pd_x12_d_d0 , Ito_pd_x12_a , Ito_pd_x13_d_d0 , Ito_pd_x13_a , Ito_pd_x14_d_d0 , Ito_pd_x14_a , Ito_pd_y0_d_d0 , Ito_pd_y0_a , Ito_pd_y1_d_d0 , Ito_pd_y1_a , Ito_pd_y2_d_d0 , Ito_pd_y2_a , Ito_pd_y3_d_d0 , Ito_pd_y3_a , Ito_pd_y4_d_d0 , Ito_pd_y4_a , Ito_pd_y5_d_d0 , Ito_pd_y5_a , Isupply_vdd , Isupply_vss , reset_B, vdd, vss);
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input vdd;
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input vss;
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input Iinx0_d_d0 ;
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input Iinx1_d_d0 ;
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input Iinx2_d_d0 ;
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input Iinx3_d_d0 ;
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input Iinx4_d_d0 ;
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input Iinx5_d_d0 ;
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input Iinx6_d_d0 ;
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input Iinx7_d_d0 ;
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input Iinx8_d_d0 ;
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input Iinx9_d_d0 ;
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input Iinx10_d_d0 ;
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input Iinx11_d_d0 ;
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input Iinx12_d_d0 ;
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input Iinx13_d_d0 ;
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input Iinx14_d_d0 ;
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input Iiny0_d_d0 ;
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input Iiny1_d_d0 ;
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input Iiny2_d_d0 ;
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input Iiny3_d_d0 ;
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input Iiny4_d_d0 ;
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input Iiny5_d_d0 ;
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input Iout_a ;
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input Iout_v ;
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input Ito_pd_x0_a ;
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input Ito_pd_x1_a ;
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input Ito_pd_x2_a ;
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input Ito_pd_x3_a ;
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input Ito_pd_x4_a ;
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input Ito_pd_x5_a ;
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input Ito_pd_x6_a ;
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input Ito_pd_x7_a ;
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input Ito_pd_x8_a ;
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input Ito_pd_x9_a ;
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input Ito_pd_x10_a ;
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input Ito_pd_x11_a ;
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input Ito_pd_x12_a ;
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input Ito_pd_x13_a ;
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input Ito_pd_x14_a ;
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input Ito_pd_y0_a ;
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input Ito_pd_y1_a ;
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input Ito_pd_y2_a ;
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input Ito_pd_y3_a ;
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input Ito_pd_y4_a ;
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input Ito_pd_y5_a ;
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input Isupply_vdd ;
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input Isupply_vss ;
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input reset_B;
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// -- signals ---
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output Iout_d_d4_d1 ;
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wire Ito_pd_x12_a ;
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output Ito_pd_x8_d_d0 ;
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wire Idly_x6_out ;
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output Iiny1_a ;
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wire Iinx5_d_d0 ;
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wire Idly_x10_in ;
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wire Iinx13_d_d0 ;
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output Iiny3_a ;
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wire Idly_x5_in ;
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wire Idly_y3_out ;
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wire Isupply_vdd ;
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wire Iinx12_d_d0 ;
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wire IXenc_out_d2_d0 ;
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output Ito_pd_x3_d_d0 ;
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output Ito_pd_y3_d_d0 ;
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wire Idly_x2_in ;
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wire _r_x ;
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wire Idly_y2_in ;
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wire Idly_x14_out ;
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wire Ito_pd_x3_a ;
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wire Ito_pd_x4_a ;
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output Iinx1_a ;
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wire Ipd_y5_reset_B ;
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wire Iinx0_d_d0 ;
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wire Idly_x0_out ;
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output Iinx11_a ;
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output Iinx14_a ;
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wire IXenc_out_d0_d0 ;
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output Iinx3_a ;
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output Iinx8_a ;
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wire Idly_x13_out ;
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wire Iout_v ;
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wire Idly_y1_out ;
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output Iout_d_d1_d1 ;
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wire Iinx8_d_d0 ;
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wire Idly_x13_in ;
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output Iout_d_d3_d0 ;
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wire IYenc_out_d0_d1 ;
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wire Idly_x3_out ;
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output Ito_pd_y2_d_d0 ;
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output Iinx2_a ;
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wire Idly_y5_in ;
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wire Ito_pd_x5_a ;
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wire Ito_pd_x7_a ;
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wire Iiny5_d_d0 ;
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output Iout_d_d6_d1 ;
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wire Idly_x8_in ;
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wire Iinx9_d_d0 ;
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output Iinx4_a ;
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output Iiny2_a ;
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wire Iiny0_d_d0 ;
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wire Idly_y3_in ;
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output Iout_d_d2_d0 ;
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wire Idly_x4_in ;
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wire IXenc_out_d1_d0 ;
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output Ito_pd_x11_d_d0 ;
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wire Idly_y1_in ;
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wire Iiny3_d_d0 ;
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output Ito_pd_x9_d_d0 ;
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wire Idly_x1_out ;
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output Iout_d_d0_d0 ;
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output Iout_d_d0_d1 ;
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wire Ibuf_in_v ;
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wire IYenc_out_d0_d0 ;
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wire Ito_pd_y4_a ;
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output Ito_pd_x1_d_d0 ;
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wire Idly_y4_out ;
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wire Iinx6_d_d0 ;
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wire Idly_x10_out ;
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output Iiny4_a ;
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wire Iinx7_d_d0 ;
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wire IYenc_out_d1_d1 ;
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output Ito_pd_x7_d_d0 ;
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output Ito_pd_y5_d_d0 ;
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wire Ito_pd_y5_a ;
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output Ito_pd_x0_d_d0 ;
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wire Ito_pd_x2_a ;
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output Iout_d_d5_d1 ;
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wire Idly_x12_in ;
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output Iinx6_a ;
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wire Idly_y5_out ;
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wire Iiny2_d_d0 ;
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output Ito_pd_x2_d_d0 ;
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output Iiny0_a ;
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wire Idly_x7_in ;
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wire Isupply_vss ;
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wire Ito_pd_x6_a ;
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wire Ito_pd_y0_a ;
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wire Idly_x14_in ;
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output Ito_pd_x10_d_d0 ;
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wire Idly_x2_out ;
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output Iiny5_a ;
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wire Iinx4_d_d0 ;
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wire IXenc_out_d3_d1 ;
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wire Idly_y2_out ;
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wire Idly_x12_out ;
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wire Ito_pd_x8_a ;
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wire IYenc_out_d1_d0 ;
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wire Idly_x3_in ;
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wire reset_B;
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output Iinx5_a ;
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wire IXenc_out_d0_d1 ;
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output Ito_pd_x14_d_d0 ;
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output Iout_d_d6_d0 ;
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wire Idly_x9_in ;
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wire Ia_x_Cel_c1 ;
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output Ito_pd_x6_d_d0 ;
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wire Ito_pd_y1_a ;
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output Ito_pd_y1_d_d0 ;
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wire Idly_x0_in ;
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output Iinx13_a ;
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wire Ito_pd_y3_a ;
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wire Iiny4_d_d0 ;
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wire IYenc_out_d2_d0 ;
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wire Iinx11_d_d0 ;
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wire Iinv_buf_a ;
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wire Idly_x11_out ;
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wire Ito_pd_x1_a ;
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wire Iinx14_d_d0 ;
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wire IXenc_out_d1_d1 ;
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wire Ito_pd_x9_a ;
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wire Ito_pd_x14_a ;
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wire Ito_pd_y2_a ;
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wire Iinx1_d_d0 ;
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wire _r_y ;
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wire Idly_y4_in ;
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wire Idly_x9_out ;
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output Ito_pd_y0_d_d0 ;
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wire Iinx10_d_d0 ;
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output Iinx7_a ;
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wire Iout_a ;
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wire IYenc_out_d2_d1 ;
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wire Ito_pd_x0_a ;
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wire Ito_pd_x13_a ;
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output Iout_d_d5_d0 ;
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wire Idly_y0_in ;
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wire Iiny1_d_d0 ;
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output Iinx12_a ;
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wire Idly_x4_out ;
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wire Idly_x11_in ;
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output Ito_pd_x5_d_d0 ;
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output Iout_d_d1_d0 ;
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wire IXenc_out_d2_d1 ;
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wire IXenc_out_d3_d0 ;
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wire Idly_y0_out ;
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output Iinx10_a ;
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wire Idly_x8_out ;
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wire Idly_x1_in ;
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wire _a_x ;
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wire Ipd_x14_reset_B ;
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output Iinx0_a ;
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output Ito_pd_x12_d_d0 ;
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wire Ito_pd_x11_a ;
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output Iout_d_d2_d1 ;
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wire Idly_x6_in ;
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output Ito_pd_x4_d_d0 ;
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output Iout_d_d3_d1 ;
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wire Iinx3_d_d0 ;
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wire _a_y ;
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wire Idly_x5_out ;
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output Iout_d_d4_d0 ;
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wire Idly_x7_out ;
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wire Ito_pd_x10_a ;
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output Ito_pd_y4_d_d0 ;
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wire Iinx2_d_d0 ;
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output Iinx9_a ;
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output Ito_pd_x13_d_d0 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0arbtree_315_4 IXarb (.Iin0_d_d0 (Iinx0_d_d0 ), .Iin0_a (Idly_x0_in ), .Iin1_d_d0 (Iinx1_d_d0 ), .Iin1_a (Idly_x1_in ), .Iin2_d_d0 (Iinx2_d_d0 ), .Iin2_a (Idly_x2_in ), .Iin3_d_d0 (Iinx3_d_d0 ), .Iin3_a (Idly_x3_in ), .Iin4_d_d0 (Iinx4_d_d0 ), .Iin4_a (Idly_x4_in ), .Iin5_d_d0 (Iinx5_d_d0 ), .Iin5_a (Idly_x5_in ), .Iin6_d_d0 (Iinx6_d_d0 ), .Iin6_a (Idly_x6_in ), .Iin7_d_d0 (Iinx7_d_d0 ), .Iin7_a (Idly_x7_in ), .Iin8_d_d0 (Iinx8_d_d0 ), .Iin8_a (Idly_x8_in ), .Iin9_d_d0 (Iinx9_d_d0 ), .Iin9_a (Idly_x9_in ), .Iin10_d_d0 (Iinx10_d_d0 ), .Iin10_a (Idly_x10_in ), .Iin11_d_d0 (Iinx11_d_d0 ), .Iin11_a (Idly_x11_in ), .Iin12_d_d0 (Iinx12_d_d0 ), .Iin12_a (Idly_x12_in ), .Iin13_d_d0 (Iinx13_d_d0 ), .Iin13_a (Idly_x13_in ), .Iin14_d_d0 (Iinx14_d_d0 ), .Iin14_a (Idly_x14_in ), .Iout_d_d0 (_r_x), .Iout_a (_a_x), .vdd(vdd), .vss(vss));
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INV_X2 Iinv_buf (.y(Ia_x_Cel_c1 ), .a(Iinv_buf_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Irsb_pd_x (.in(reset_B), .Iout0 (Ipd_x14_reset_B ), .vdd(vdd), .vss(vss));
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A_2C_RB_X1 Ia_y_Cel (.y(_a_y), .c1(Ia_x_Cel_c1 ), .c2(_r_y), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0dualrail__encoder_34_715_4 IXenc (.Iin0 (Iinx0_a ), .Iin1 (Iinx1_a ), .Iin2 (Iinx2_a ), .Iin3 (Iinx3_a ), .Iin4 (Iinx4_a ), .Iin5 (Iinx5_a ), .Iin6 (Iinx6_a ), .Iin7 (Iinx7_a ), .Iin8 (Iinx8_a ), .Iin9 (Iinx9_a ), .Iin10 (Iinx10_a ), .Iin11 (Iinx11_a ), .Iin12 (Iinx12_a ), .Iin13 (Iinx13_a ), .Iin14 (Iinx14_a ), .Iout_d0_d0 (IXenc_out_d0_d0 ), .Iout_d0_d1 (IXenc_out_d0_d1 ), .Iout_d1_d0 (IXenc_out_d1_d0 ), .Iout_d1_d1 (IXenc_out_d1_d1 ), .Iout_d2_d0 (IXenc_out_d2_d0 ), .Iout_d2_d1 (IXenc_out_d2_d1 ), .Iout_d3_d0 (IXenc_out_d3_d0 ), .Iout_d3_d1 (IXenc_out_d3_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x0 (.y(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x1 (.y(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x2 (.y(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x3 (.y(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x4 (.y(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x5 (.y(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x6 (.y(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x7 (.y(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x8 (.y(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x9 (.y(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x10 (.y(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x11 (.y(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x12 (.y(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x13 (.y(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_x14 (.y(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y0 (.out(Idly_y0_out ), .in(Idly_y0_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y1 (.out(Idly_y1_out ), .in(Idly_y1_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y2 (.out(Idly_y2_out ), .in(Idly_y2_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y3 (.out(Idly_y3_out ), .in(Idly_y3_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y4 (.out(Idly_y4_out ), .in(Idly_y4_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_y5 (.out(Idly_y5_out ), .in(Idly_y5_in ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a0 (.y(Iinx0_a ), .a(Idly_x0_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a1 (.y(Iinx1_a ), .a(Idly_x1_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a2 (.y(Iinx2_a ), .a(Idly_x2_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a3 (.y(Iinx3_a ), .a(Idly_x3_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a4 (.y(Iinx4_a ), .a(Idly_x4_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a5 (.y(Iinx5_a ), .a(Idly_x5_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a6 (.y(Iinx6_a ), .a(Idly_x6_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a7 (.y(Iinx7_a ), .a(Idly_x7_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a8 (.y(Iinx8_a ), .a(Idly_x8_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a9 (.y(Iinx9_a ), .a(Idly_x9_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a10 (.y(Iinx10_a ), .a(Idly_x10_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a11 (.y(Iinx11_a ), .a(Idly_x11_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a12 (.y(Iinx12_a ), .a(Idly_x12_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a13 (.y(Iinx13_a ), .a(Idly_x13_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_inx_a14 (.y(Iinx14_a ), .a(Idly_x14_out ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x0 (.in(Ito_pd_x0_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x0_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x1 (.in(Ito_pd_x1_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x1_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x2 (.in(Ito_pd_x2_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x2_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x3 (.in(Ito_pd_x3_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x3_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x4 (.in(Ito_pd_x4_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x4_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x5 (.in(Ito_pd_x5_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x5_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x6 (.in(Ito_pd_x6_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x6_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x7 (.in(Ito_pd_x7_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x7_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x8 (.in(Ito_pd_x8_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x8_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x9 (.in(Ito_pd_x9_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x9_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x10 (.in(Ito_pd_x10_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x10_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x11 (.in(Ito_pd_x11_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x11_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x12 (.in(Ito_pd_x12_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x12_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x13 (.in(Ito_pd_x13_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x13_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_x14 (.in(Ito_pd_x14_a ), .reset_B(Ipd_x14_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_x14_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y0 (.in(Ito_pd_y0_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y1 (.in(Ito_pd_y1_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y2 (.in(Ito_pd_y2_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y3 (.in(Ito_pd_y3_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y4 (.in(Ito_pd_y4_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down Ipd_y5 (.in(Ito_pd_y5_a ), .reset_B(Ipd_y5_reset_B ), .Isupply_vdd (Isupply_vdd ), .out(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0buffer_37_4 Ibuf (.Iin_d_d0_d0 (IXenc_out_d0_d0 ), .Iin_d_d0_d1 (IXenc_out_d0_d1 ), .Iin_d_d1_d0 (IXenc_out_d1_d0 ), .Iin_d_d1_d1 (IXenc_out_d1_d1 ), .Iin_d_d2_d0 (IXenc_out_d2_d0 ), .Iin_d_d2_d1 (IXenc_out_d2_d1 ), .Iin_d_d3_d0 (IXenc_out_d3_d0 ), .Iin_d_d3_d1 (IXenc_out_d3_d1 ), .Iin_d_d4_d0 (IYenc_out_d0_d0 ), .Iin_d_d4_d1 (IYenc_out_d0_d1 ), .Iin_d_d5_d0 (IYenc_out_d1_d0 ), .Iin_d_d5_d1 (IYenc_out_d1_d1 ), .Iin_d_d6_d0 (IYenc_out_d2_d0 ), .Iin_d_d6_d1 (IYenc_out_d2_d1 ), .Iin_a (Iinv_buf_a ), .Iin_v (Ibuf_in_v ), .Iout_d_d0_d0 (Iout_d_d0_d0 ), .Iout_d_d0_d1 (Iout_d_d0_d1 ), .Iout_d_d1_d0 (Iout_d_d1_d0 ), .Iout_d_d1_d1 (Iout_d_d1_d1 ), .Iout_d_d2_d0 (Iout_d_d2_d0 ), .Iout_d_d2_d1 (Iout_d_d2_d1 ), .Iout_d_d3_d0 (Iout_d_d3_d0 ), .Iout_d_d3_d1 (Iout_d_d3_d1 ), .Iout_d_d4_d0 (Iout_d_d4_d0 ), .Iout_d_d4_d1 (Iout_d_d4_d1 ), .Iout_d_d5_d0 (Iout_d_d5_d0 ), .Iout_d_d5_d1 (Iout_d_d5_d1 ), .Iout_d_d6_d0 (Iout_d_d6_d0 ), .Iout_d_d6_d1 (Iout_d_d6_d1 ), .Iout_a (Iout_a ), .Iout_v (Iout_v ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x0 (.out(Idly_x0_out ), .in(Idly_x0_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x1 (.out(Idly_x1_out ), .in(Idly_x1_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x2 (.out(Idly_x2_out ), .in(Idly_x2_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x3 (.out(Idly_x3_out ), .in(Idly_x3_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x4 (.out(Idly_x4_out ), .in(Idly_x4_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x5 (.out(Idly_x5_out ), .in(Idly_x5_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x6 (.out(Idly_x6_out ), .in(Idly_x6_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x7 (.out(Idly_x7_out ), .in(Idly_x7_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x8 (.out(Idly_x8_out ), .in(Idly_x8_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x9 (.out(Idly_x9_out ), .in(Idly_x9_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x10 (.out(Idly_x10_out ), .in(Idly_x10_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x11 (.out(Idly_x11_out ), .in(Idly_x11_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x12 (.out(Idly_x12_out ), .in(Idly_x12_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x13 (.out(Idly_x13_out ), .in(Idly_x13_in ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0delay__chain_32_4 Idly_x14 (.out(Idly_x14_out ), .in(Idly_x14_in ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y0 (.y(Ito_pd_y0_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y1 (.y(Ito_pd_y1_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y2 (.y(Ito_pd_y2_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y3 (.y(Ito_pd_y3_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y4 (.y(Ito_pd_y4_d_d0 ), .vdd(vdd), .vss(vss));
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KEEP Ikeep_y5 (.y(Ito_pd_y5_d_d0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbtree_36_4 IYarb (.Iin0_d_d0 (Iiny0_d_d0 ), .Iin0_a (Idly_y0_in ), .Iin1_d_d0 (Iiny1_d_d0 ), .Iin1_a (Idly_y1_in ), .Iin2_d_d0 (Iiny2_d_d0 ), .Iin2_a (Idly_y2_in ), .Iin3_d_d0 (Iiny3_d_d0 ), .Iin3_a (Idly_y3_in ), .Iin4_d_d0 (Iiny4_d_d0 ), .Iin4_a (Idly_y4_in ), .Iin5_d_d0 (Iiny5_d_d0 ), .Iin5_a (Idly_y5_in ), .Iout_d_d0 (_r_y), .Iout_a (_a_y), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0dualrail__encoder_33_76_4 IYenc (.Iin0 (Iiny0_a ), .Iin1 (Iiny1_a ), .Iin2 (Iiny2_a ), .Iin3 (Iiny3_a ), .Iin4 (Iiny4_a ), .Iin5 (Iiny5_a ), .Iout_d0_d0 (IYenc_out_d0_d0 ), .Iout_d0_d1 (IYenc_out_d0_d1 ), .Iout_d1_d0 (IYenc_out_d1_d0 ), .Iout_d1_d1 (IYenc_out_d1_d1 ), .Iout_d2_d0 (IYenc_out_d2_d0 ), .Iout_d2_d1 (IYenc_out_d2_d1 ), .Isupply_vss (Isupply_vss ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a0 (.y(Iiny0_a ), .a(Idly_y0_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a1 (.y(Iiny1_a ), .a(Idly_y1_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a2 (.y(Iiny2_a ), .a(Idly_y2_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a3 (.y(Iiny3_a ), .a(Idly_y3_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a4 (.y(Iiny4_a ), .a(Idly_y4_out ), .vdd(vdd), .vss(vss));
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BUF_X12 Isb_iny_a5 (.y(Iiny5_a ), .a(Idly_y5_out ), .vdd(vdd), .vss(vss));
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A_2C_RB_X1 Ia_x_Cel (.y(_a_x), .c1(Ia_x_Cel_c1 ), .c2(_r_x), .pr_B(reset_B), .sr_B(reset_B), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_36_4 Irsb_pd_y (.in(reset_B), .Iout0 (Ipd_y5_reset_B ), .vdd(vdd), .vss(vss));
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endmodule |