37 lines
1.3 KiB
Verilog
37 lines
1.3 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(Iin_d_d0 , Iin_a , Ioutx_d_d0 , Ioutx_a , Iouty_d_d0 , Iouty_a , reset_B, vdd, vss);
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input vdd;
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input vss;
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input Iin_d_d0 ;
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input Ioutx_a ;
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input Iouty_a ;
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input reset_B;
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// -- signals ---
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wire reset_B;
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wire _en ;
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wire Iin_d_d0 ;
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output Iin_a ;
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wire _reqB ;
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output Iouty_d_d0 ;
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output Ioutx_d_d0 ;
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wire _y_a_B ;
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wire _x_a_B ;
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wire Ioutx_a ;
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wire Iouty_a ;
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wire _reset_BX ;
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wire _req ;
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// --- instances
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INV_X1 Ireq_inv (.y(_reqB), .a(_req), .vdd(vdd), .vss(vss));
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A_2P_U_X4 Ipu_y (.p1(Iouty_a ), .p2(_reqB), .y(Iouty_d_d0 ), .vdd(vdd), .vss(vss));
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INV_X2 Iinv_x (.y(_x_a_B), .a(Ioutx_a ), .vdd(vdd), .vss(vss));
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INV_X2 Iinv_y (.y(_y_a_B), .a(Iouty_a ), .vdd(vdd), .vss(vss));
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A_2C1N_RB_X1 IA_ack (.y(Iin_a ), .c1(_en), .c2(Iin_d_d0 ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
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BUF_X2 Ireset_buf (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
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A_1C1P_X1 IA_en (.y(_en), .c1(Iin_a ), .p1(_req), .vdd(vdd), .vss(vss));
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A_2C1P1N_RB_X1 IA_req (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(Iin_d_d0 ), .pr_B(_reset_BX), .sr_B(_reset_BX), .vdd(vdd), .vss(vss));
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A_3P_U_X4 Ipu_x (.p1(Ioutx_a ), .p2(_y_a_B), .p3(_reqB), .y(Ioutx_d_d0 ), .vdd(vdd), .vss(vss));
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endmodule |