22 lines
634 B
Verilog
22 lines
634 B
Verilog
module tmpl_0_0dataflow__neuro_0_0nrn__line__end__pull__down(in, reset_B, Isupply_vdd , out, vdd, vss);
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input vdd;
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input vss;
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input in;
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input reset_B;
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input Isupply_vdd ;
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output out;
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// -- signals ---
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wire Iinv_y ;
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wire Itiehi_y ;
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wire reset_B;
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wire in;
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wire Isupply_vdd ;
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wire out ;
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// --- instances
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A_2N_U_X4 Ipull_down (.n1(in), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
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TIEHI_X1 Itiehi (.y(Itiehi_y ), .vdd(vdd), .vss(vss));
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A_2N_U_X4 Ipull_downR (.n1(Iinv_y ), .n2(Itiehi_y ), .y(out), .vdd(vdd), .vss(vss));
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INV_X1 Iinv (.y(Iinv_y ), .a(reset_B), .vdd(vdd), .vss(vss));
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endmodule |