49 lines
1.9 KiB
Verilog
49 lines
1.9 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0arbtree_36_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iout_d_d0 , Iout_a , vdd, vss);
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input vdd;
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input vss;
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input Iin0_d_d0 ;
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input Iin1_d_d0 ;
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input Iin2_d_d0 ;
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input Iin3_d_d0 ;
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input Iin4_d_d0 ;
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input Iin5_d_d0 ;
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input Iout_a ;
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// -- signals ---
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wire Itmp6_d_d0 ;
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wire Itmp9_d_d0 ;
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output Iin0_a ;
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output Iout_d_d0 ;
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wire Iin1_d_d0 ;
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wire Itmp6_a ;
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wire Iin0_d_d0 ;
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wire Itmp7_d_d0 ;
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output Iin5_a ;
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wire Iin4_d_d0 ;
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wire Itmp10_a ;
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wire Itmp7_a ;
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wire Iin2_d_d0 ;
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output Iin1_a ;
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wire Itmp9_a ;
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wire Iin5_d_d0 ;
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output Iin3_a ;
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wire Iin3_d_d0 ;
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wire Itmp10_d_d0 ;
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output Iin4_a ;
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output Iin2_a ;
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wire Iout_a ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs0 (.Iin1_d_d0 (Iin0_d_d0 ), .Iin1_a (Iin0_a ), .Iin2_d_d0 (Iin1_d_d0 ), .Iin2_a (Iin1_a ), .Iout_d_d0 (Itmp6_d_d0 ), .Iout_a (Itmp6_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs1 (.Iin1_d_d0 (Iin2_d_d0 ), .Iin1_a (Iin2_a ), .Iin2_d_d0 (Iin3_d_d0 ), .Iin2_a (Iin3_a ), .Iout_d_d0 (Itmp7_d_d0 ), .Iout_a (Itmp7_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs2 (.Iin1_d_d0 (Iin4_d_d0 ), .Iin1_a (Iin4_a ), .Iin2_d_d0 (Iin5_d_d0 ), .Iin2_a (Iin5_a ), .Iout_d_d0 (Itmp10_d_d0 ), .Iout_a (Itmp10_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs3 (.Iin1_d_d0 (Itmp6_d_d0 ), .Iin1_a (Itmp6_a ), .Iin2_d_d0 (Itmp7_d_d0 ), .Iin2_a (Itmp7_a ), .Iout_d_d0 (Itmp9_d_d0 ), .Iout_a (Itmp9_a ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0arbiter__handshake Iarbs4 (.Iin1_d_d0 (Itmp9_d_d0 ), .Iin1_a (Itmp9_a ), .Iin2_d_d0 (Itmp10_d_d0 ), .Iin2_a (Itmp10_a ), .Iout_d_d0 (Iout_d_d0 ), .Iout_a (Iout_a ), .vdd(vdd), .vss(vss));
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endmodule |