101 lines
3.2 KiB
Verilog
101 lines
3.2 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0ctree_324_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , out, vdd, vss);
|
|
input vdd;
|
|
input vss;
|
|
input Iin0 ;
|
|
input Iin1 ;
|
|
input Iin2 ;
|
|
input Iin3 ;
|
|
input Iin4 ;
|
|
input Iin5 ;
|
|
input Iin6 ;
|
|
input Iin7 ;
|
|
input Iin8 ;
|
|
input Iin9 ;
|
|
input Iin10 ;
|
|
input Iin11 ;
|
|
input Iin12 ;
|
|
input Iin13 ;
|
|
input Iin14 ;
|
|
input Iin15 ;
|
|
input Iin16 ;
|
|
input Iin17 ;
|
|
input Iin18 ;
|
|
input Iin19 ;
|
|
input Iin20 ;
|
|
input Iin21 ;
|
|
input Iin22 ;
|
|
input Iin23 ;
|
|
output out;
|
|
|
|
// -- signals ---
|
|
wire Itmp35 ;
|
|
wire Itmp27 ;
|
|
wire Iin2 ;
|
|
wire Itmp38 ;
|
|
wire Iin21 ;
|
|
wire Iin12 ;
|
|
wire Iin1 ;
|
|
wire Iin16 ;
|
|
wire Iin20 ;
|
|
wire Itmp32 ;
|
|
wire Itmp40 ;
|
|
wire Itmp44 ;
|
|
wire Iin17 ;
|
|
wire Iin14 ;
|
|
wire Iin8 ;
|
|
wire Itmp28 ;
|
|
wire Itmp29 ;
|
|
wire Iin0 ;
|
|
wire Itmp24 ;
|
|
wire Itmp33 ;
|
|
wire Itmp42 ;
|
|
wire Itmp34 ;
|
|
wire Itmp41 ;
|
|
wire Iin11 ;
|
|
wire Iin10 ;
|
|
wire Iin4 ;
|
|
wire Itmp31 ;
|
|
wire Iin19 ;
|
|
wire Itmp36 ;
|
|
wire Iin9 ;
|
|
wire Iin23 ;
|
|
wire Iin13 ;
|
|
wire Iin5 ;
|
|
wire Iin18 ;
|
|
wire out ;
|
|
wire Iin7 ;
|
|
wire Itmp25 ;
|
|
wire Itmp37 ;
|
|
wire Iin6 ;
|
|
wire Itmp26 ;
|
|
wire Iin3 ;
|
|
wire Itmp43 ;
|
|
wire Itmp39 ;
|
|
wire Iin22 ;
|
|
wire Iin15 ;
|
|
wire Itmp30 ;
|
|
|
|
// --- instances
|
|
A_2C_B_X1 IC2Els0 (.y(Itmp24 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els1 (.y(Itmp25 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els2 (.y(Itmp26 ), .c1(Iin4 ), .c2(Iin5 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els3 (.y(Itmp27 ), .c1(Iin6 ), .c2(Iin7 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els4 (.y(Itmp28 ), .c1(Iin8 ), .c2(Iin9 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els5 (.y(Itmp29 ), .c1(Iin10 ), .c2(Iin11 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els6 (.y(Itmp30 ), .c1(Iin12 ), .c2(Iin13 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els7 (.y(Itmp31 ), .c1(Iin14 ), .c2(Iin15 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els8 (.y(Itmp32 ), .c1(Iin16 ), .c2(Iin17 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els9 (.y(Itmp33 ), .c1(Iin18 ), .c2(Iin19 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els10 (.y(Itmp34 ), .c1(Iin20 ), .c2(Iin21 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els11 (.y(Itmp35 ), .c1(Iin22 ), .c2(Iin23 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els12 (.y(Itmp36 ), .c1(Itmp24 ), .c2(Itmp25 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els13 (.y(Itmp37 ), .c1(Itmp26 ), .c2(Itmp27 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els14 (.y(Itmp38 ), .c1(Itmp28 ), .c2(Itmp29 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els15 (.y(Itmp39 ), .c1(Itmp30 ), .c2(Itmp31 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els16 (.y(Itmp40 ), .c1(Itmp32 ), .c2(Itmp33 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els17 (.y(Itmp41 ), .c1(Itmp34 ), .c2(Itmp35 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els18 (.y(Itmp42 ), .c1(Itmp36 ), .c2(Itmp37 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els19 (.y(Itmp43 ), .c1(Itmp38 ), .c2(Itmp39 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els20 (.y(Itmp44 ), .c1(Itmp40 ), .c2(Itmp41 ), .vdd(vdd), .vss(vss));
|
|
A_3C_B_X1 IC3Els0 (.y(out), .c1(Itmp42 ), .c2(Itmp43 ), .c3(Itmp44 ), .vdd(vdd), .vss(vss));
|
|
endmodule |