31 lines
819 B
Verilog
31 lines
819 B
Verilog
module tmpl_0_0dataflow__neuro_0_0ctree_37_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , out, vdd, vss);
|
|
input vdd;
|
|
input vss;
|
|
input Iin0 ;
|
|
input Iin1 ;
|
|
input Iin2 ;
|
|
input Iin3 ;
|
|
input Iin4 ;
|
|
input Iin5 ;
|
|
input Iin6 ;
|
|
output out;
|
|
|
|
// -- signals ---
|
|
wire Iin5 ;
|
|
wire Itmp9 ;
|
|
wire Iin4 ;
|
|
wire Itmp8 ;
|
|
wire Iin2 ;
|
|
wire Iin6 ;
|
|
wire Iin1 ;
|
|
wire Iin0 ;
|
|
wire Iin3 ;
|
|
wire Itmp7 ;
|
|
wire out ;
|
|
|
|
// --- instances
|
|
A_2C_B_X1 IC2Els0 (.y(Itmp7 ), .c1(Iin0 ), .c2(Iin1 ), .vdd(vdd), .vss(vss));
|
|
A_2C_B_X1 IC2Els1 (.y(Itmp8 ), .c1(Iin2 ), .c2(Iin3 ), .vdd(vdd), .vss(vss));
|
|
A_3C_B_X1 IC3Els0 (.y(Itmp9 ), .c1(Iin4 ), .c2(Iin5 ), .c3(Iin6 ), .vdd(vdd), .vss(vss));
|
|
A_3C_B_X1 IC3Els1 (.y(out), .c1(Itmp7 ), .c2(Itmp8 ), .c3(Itmp9 ), .vdd(vdd), .vss(vss));
|
|
endmodule |