actlib_dataflow_neuro/dataflow_neuro/cell_lib_std.act

/*************************************************************************
 *
 *  This file is part of ACT dataflow neuro library
 *
 *  Copyright (c) 2020-2021 Rajit Manohar
 *  Copyright (c) 2022 University of Groningen - Ole Richter  
 *  Copyright (c) 2022 University of Groningen - Madison Cotteret
 *
 *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
 *
 *  You may redistribute and modify this documentation and make products
 *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
 *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
 *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
 *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
 *  for applicable conditions.
 *
 *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
 *
 *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
 *  these sources, You must maintain the Source Location visible in its
 *  documentation.
 *
 **************************************************************************
 */

namespace template {
  namespace dataflow_neuro {

    export defproc TIELO_X1(bool! y; bool? vdd, vss)
    {
      y = vss;
    }

    export defproc TIEHI_X1(bool! y; bool? vdd, vss)
    {
      y = vdd;
    }

    /*-- inverters --*/

    defproc inv (bool! y; bool? a, vdd, vss)
    {
      prs {
        a => y-
      }
    }
      
    template<pint nf>
    defproc szinv <: inv()
    {
      [nf = 0 -> sizing { y {-1} }
      [] else -> sizing { y {-2*nf,svt,nf} }
      ]
    }

    export defcell INV_X1<: szinv<0>() { } 
    export defcell INV_X2<: szinv<1>() { } 
    export defcell INV_X4<: szinv<2>() { }
    export defcell INV_X8<: szinv<4>() { }

    /*-- clock delay buffers --*/

    template<pint N>
    defproc dbuf (bool! y; bool? a, vdd, vss)
    {
      {N > 0 : "Delay buffer needs at least one stage!"};
      bool sig[2*N+1];
      sig[0] = a;
      sig[2*N] = y;
      prs {
        (i:2*N: ~sig[i] <80;2> -> sig[i+1]+
                sig[i] <40;2> -> sig[i+1]-
        )
      }
    }

    export defproc CLKBUF1 <: dbuf<2>() { }
    export defproc CLKBUF2 <: dbuf<3>() { }
    export defproc CLKBUF3 <: dbuf<4>() { }


    /*--  signal buffers --*/

    defproc buf (bool! y; bool? a, vdd, vss)
    {
      bool _y;
      prs {
        a => _y-
      _y => y-
      }
    }
      
    export defcell BUF_X2<: buf()
    {
      sizing { _y {-1}; y {-2} }
    }
      
    export defcell BUF_X4<: buf()
    {
      sizing { _y {-1.5}; y {-4,2} }
    }

      
    /*-- simple gates --*/
      
    export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
    {
      prs {
        a | b => y-
      }
      sizing { y {-1} }
    }
      
    export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
    {
      prs {
        a | b | c => y-
      }
      sizing { y {-1} }
    } 

    export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
    {
      bool _y;
      prs {
        a | b => _y-
        _y => y-
      }
      sizing { _y{-1}; y{-1} }
    }
      
    export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
    {
      bool _y;
      prs {
        a | b => _y-
        _y => y-
      }
      sizing { _y{-1}; y{-2} }
    } 

    export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
    {
      prs {  
        a & b => y-
      }
      sizing { y{-1} }
    }
      
    export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
    {
      prs {  
        a & b & c => y-
      }
      sizing { y{-1} }
    }

    export defcell AND2_X1(bool! y; bool? a, b, vdd, vss) 
    {
      bool _y;
      prs {  
        a & b => _y- 
      _y => y-
      }
      sizing { _y{-1}; y{-1} }
    } 

    export defcell AND2_X2(bool! y; bool? a, b, vdd, vss) 
    { 
      bool _y;
      prs {
        a & b => _y-
      _y => y-
      }
      sizing { _y{-1}; y{-2} }
    } 

    export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
    {
      bool _a, _b;
      prs {
        a => _a-
        b => _b-

        [keeper=0] ~b & ~_a | ~_b & ~a -> y+
        _b & _a | b & a -> y-
      }
      sizing { _a{-1}; _b{-1}; y{-1} }
    }

    export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
    {
      bool _a, _b;
      prs {
        a => _a-
        b => _b-

        [keeper=0] ~b & ~a | ~_b & ~_a -> y+
        b & _a | _b & a -> y-
      }
      sizing { _a{-1}; _b{-1}; y{-1} }
    }

    export defcell MUX2_X1(bool! y; bool? a, b, S, vdd, vss)
    {
      // y = !( S ? a : b )
      bool _S;
      prs {
        S => _S-

        [keeper=0] ~a & ~_S | ~b & ~S -> y+
        a & S | b & _S -> y-
      }
      sizing { _S{-1}; y{-1} }
    }

    export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
    {
      prs {
        (a | b) & c => y-  
      }
      sizing { y{-1} }
    }

    export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss) 
    { 
      prs {
        a & b | c => y-
      }
      sizing { y{-1} }
    }

    export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
    {
      // y = !((a|b) & (c|d))
      prs {
        (a | b) & (c | d) => y-  
      }
      sizing { y{-1} }
    }

    export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss) 
    { 
      prs {
        a & b | c & d => y-
      }
      sizing { y{-1} }
    }


    /*--- buffered transmission gates ---*/
      
    export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
    {
      bool _en;
      prs {
        en => _en-

      ~a & ~_en -> y+
        a & en -> y-
      }
      sizing { _en{-1}; y{-1} }
    }
    
    export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
    {
      bool _en;
      prs {
        en => _en-

      ~a & ~_en -> y+
        a & en -> y-
      }
      sizing { _en{-2}; y{-2,2} }
    }
  }
}