actlib_dataflow_neuro/test/unit_tests/register_write/run/test.prs

= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
= "t._supply.vss" "t.registers.supply.vss"
= "t._supply.vdd" "t.registers.supply.vdd"
= "Vdd" "t._supply.vdd"
= "GND" "t._supply.vss"
= "t._reset_B" "t.registers.reset_mem_B"
= "t._reset_B" "t.registers.reset_B"
= "t.data[0].d[0]" "t.registers.data[0].d[0]"
= "t.data[1].d[0]" "t.registers.data[1].d[0]"
= "t.data[2].d[0]" "t.registers.data[2].d[0]"
= "t.data[3].d[0]" "t.registers.data[3].d[0]"
= "t.data[0].d[1]" "t.registers.data[0].d[1]"
= "t.data[1].d[1]" "t.registers.data[1].d[1]"
= "t.data[2].d[1]" "t.registers.data[2].d[1]"
= "t.data[3].d[1]" "t.registers.data[3].d[1]"
= "t.registers._clock_temp" "t.registers.inv_clk.a"
= "t.registers._clock_temp" "t.registers.clk_dly.out"
"t.registers.reset_bufarray.buf3.a"->"t.registers.reset_bufarray.buf3._y"-
~("t.registers.reset_bufarray.buf3.a")->"t.registers.reset_bufarray.buf3._y"+
"t.registers.reset_bufarray.buf3._y"->"t.registers.reset_bufarray.buf3.y"-
~("t.registers.reset_bufarray.buf3._y")->"t.registers.reset_bufarray.buf3.y"+
= "t.registers.reset_bufarray.supply.vdd" "t.registers.reset_bufarray.buf3.vdd"
= "t.registers.reset_bufarray.supply.vss" "t.registers.reset_bufarray.buf3.vss"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[7]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[6]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[5]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[4]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[3]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[2]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.out[1]"
= "t.registers.reset_bufarray.out[0]" "t.registers.reset_bufarray.buf3.y"
= "t.registers.reset_bufarray.in" "t.registers.reset_bufarray.buf3.a"
"t.registers.ff[0].clk_B"->"t.registers.ff[0]._clk_B"-
~("t.registers.ff[0].clk_B")->"t.registers.ff[0]._clk_B"+
"t.registers.ff[0]._clk_B"->"t.registers.ff[0].__clk_B"-
~("t.registers.ff[0]._clk_B")->"t.registers.ff[0].__clk_B"+
~"t.registers.ff[0].d"&~"t.registers.ff[0]._clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0].__clk_B"&~"t.registers.ff[0]._mqi"->"t.registers.ff[0]._mqib"+
("t.registers.ff[0].d"&"t.registers.ff[0].__clk_B"|"t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._mqib"-
"t.registers.ff[0]._mqib"->"t.registers.ff[0]._mqi"-
~("t.registers.ff[0]._mqib")->"t.registers.ff[0]._mqi"+
~"t.registers.ff[0]._mqi"&~"t.registers.ff[0].__clk_B"|~"t.registers.ff[0].reset_B"|~"t.registers.ff[0]._sqi"&~"t.registers.ff[0]._clk_B"->"t.registers.ff[0]._sqib"+
("t.registers.ff[0]._mqi"&"t.registers.ff[0]._clk_B"|"t.registers.ff[0]._sqi"&"t.registers.ff[0].__clk_B")&"t.registers.ff[0].reset_B"->"t.registers.ff[0]._sqib"-
"t.registers.ff[0]._sqib"->"t.registers.ff[0]._sqi"-
~("t.registers.ff[0]._sqib")->"t.registers.ff[0]._sqi"+
"t.registers.ff[0]._sqib"->"t.registers.ff[0].q"-
~("t.registers.ff[0]._sqib")->"t.registers.ff[0].q"+
"t.registers.ff[1].clk_B"->"t.registers.ff[1]._clk_B"-
~("t.registers.ff[1].clk_B")->"t.registers.ff[1]._clk_B"+
"t.registers.ff[1]._clk_B"->"t.registers.ff[1].__clk_B"-
~("t.registers.ff[1]._clk_B")->"t.registers.ff[1].__clk_B"+
~"t.registers.ff[1].d"&~"t.registers.ff[1]._clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1].__clk_B"&~"t.registers.ff[1]._mqi"->"t.registers.ff[1]._mqib"+
("t.registers.ff[1].d"&"t.registers.ff[1].__clk_B"|"t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._mqib"-
"t.registers.ff[1]._mqib"->"t.registers.ff[1]._mqi"-
~("t.registers.ff[1]._mqib")->"t.registers.ff[1]._mqi"+
~"t.registers.ff[1]._mqi"&~"t.registers.ff[1].__clk_B"|~"t.registers.ff[1].reset_B"|~"t.registers.ff[1]._sqi"&~"t.registers.ff[1]._clk_B"->"t.registers.ff[1]._sqib"+
("t.registers.ff[1]._mqi"&"t.registers.ff[1]._clk_B"|"t.registers.ff[1]._sqi"&"t.registers.ff[1].__clk_B")&"t.registers.ff[1].reset_B"->"t.registers.ff[1]._sqib"-
"t.registers.ff[1]._sqib"->"t.registers.ff[1]._sqi"-
~("t.registers.ff[1]._sqib")->"t.registers.ff[1]._sqi"+
"t.registers.ff[1]._sqib"->"t.registers.ff[1].q"-
~("t.registers.ff[1]._sqib")->"t.registers.ff[1].q"+
"t.registers.ff[2].clk_B"->"t.registers.ff[2]._clk_B"-
~("t.registers.ff[2].clk_B")->"t.registers.ff[2]._clk_B"+
"t.registers.ff[2]._clk_B"->"t.registers.ff[2].__clk_B"-
~("t.registers.ff[2]._clk_B")->"t.registers.ff[2].__clk_B"+
~"t.registers.ff[2].d"&~"t.registers.ff[2]._clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2].__clk_B"&~"t.registers.ff[2]._mqi"->"t.registers.ff[2]._mqib"+
("t.registers.ff[2].d"&"t.registers.ff[2].__clk_B"|"t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._mqib"-
"t.registers.ff[2]._mqib"->"t.registers.ff[2]._mqi"-
~("t.registers.ff[2]._mqib")->"t.registers.ff[2]._mqi"+
~"t.registers.ff[2]._mqi"&~"t.registers.ff[2].__clk_B"|~"t.registers.ff[2].reset_B"|~"t.registers.ff[2]._sqi"&~"t.registers.ff[2]._clk_B"->"t.registers.ff[2]._sqib"+
("t.registers.ff[2]._mqi"&"t.registers.ff[2]._clk_B"|"t.registers.ff[2]._sqi"&"t.registers.ff[2].__clk_B")&"t.registers.ff[2].reset_B"->"t.registers.ff[2]._sqib"-
"t.registers.ff[2]._sqib"->"t.registers.ff[2]._sqi"-
~("t.registers.ff[2]._sqib")->"t.registers.ff[2]._sqi"+
"t.registers.ff[2]._sqib"->"t.registers.ff[2].q"-
~("t.registers.ff[2]._sqib")->"t.registers.ff[2].q"+
"t.registers.ff[3].clk_B"->"t.registers.ff[3]._clk_B"-
~("t.registers.ff[3].clk_B")->"t.registers.ff[3]._clk_B"+
"t.registers.ff[3]._clk_B"->"t.registers.ff[3].__clk_B"-
~("t.registers.ff[3]._clk_B")->"t.registers.ff[3].__clk_B"+
~"t.registers.ff[3].d"&~"t.registers.ff[3]._clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3].__clk_B"&~"t.registers.ff[3]._mqi"->"t.registers.ff[3]._mqib"+
("t.registers.ff[3].d"&"t.registers.ff[3].__clk_B"|"t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._mqib"-
"t.registers.ff[3]._mqib"->"t.registers.ff[3]._mqi"-
~("t.registers.ff[3]._mqib")->"t.registers.ff[3]._mqi"+
~"t.registers.ff[3]._mqi"&~"t.registers.ff[3].__clk_B"|~"t.registers.ff[3].reset_B"|~"t.registers.ff[3]._sqi"&~"t.registers.ff[3]._clk_B"->"t.registers.ff[3]._sqib"+
("t.registers.ff[3]._mqi"&"t.registers.ff[3]._clk_B"|"t.registers.ff[3]._sqi"&"t.registers.ff[3].__clk_B")&"t.registers.ff[3].reset_B"->"t.registers.ff[3]._sqib"-
"t.registers.ff[3]._sqib"->"t.registers.ff[3]._sqi"-
~("t.registers.ff[3]._sqib")->"t.registers.ff[3]._sqi"+
"t.registers.ff[3]._sqib"->"t.registers.ff[3].q"-
~("t.registers.ff[3]._sqib")->"t.registers.ff[3].q"+
"t.registers.ff[4].clk_B"->"t.registers.ff[4]._clk_B"-
~("t.registers.ff[4].clk_B")->"t.registers.ff[4]._clk_B"+
"t.registers.ff[4]._clk_B"->"t.registers.ff[4].__clk_B"-
~("t.registers.ff[4]._clk_B")->"t.registers.ff[4].__clk_B"+
~"t.registers.ff[4].d"&~"t.registers.ff[4]._clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4].__clk_B"&~"t.registers.ff[4]._mqi"->"t.registers.ff[4]._mqib"+
("t.registers.ff[4].d"&"t.registers.ff[4].__clk_B"|"t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._mqib"-
"t.registers.ff[4]._mqib"->"t.registers.ff[4]._mqi"-
~("t.registers.ff[4]._mqib")->"t.registers.ff[4]._mqi"+
~"t.registers.ff[4]._mqi"&~"t.registers.ff[4].__clk_B"|~"t.registers.ff[4].reset_B"|~"t.registers.ff[4]._sqi"&~"t.registers.ff[4]._clk_B"->"t.registers.ff[4]._sqib"+
("t.registers.ff[4]._mqi"&"t.registers.ff[4]._clk_B"|"t.registers.ff[4]._sqi"&"t.registers.ff[4].__clk_B")&"t.registers.ff[4].reset_B"->"t.registers.ff[4]._sqib"-
"t.registers.ff[4]._sqib"->"t.registers.ff[4]._sqi"-
~("t.registers.ff[4]._sqib")->"t.registers.ff[4]._sqi"+
"t.registers.ff[4]._sqib"->"t.registers.ff[4].q"-
~("t.registers.ff[4]._sqib")->"t.registers.ff[4].q"+
"t.registers.ff[5].clk_B"->"t.registers.ff[5]._clk_B"-
~("t.registers.ff[5].clk_B")->"t.registers.ff[5]._clk_B"+
"t.registers.ff[5]._clk_B"->"t.registers.ff[5].__clk_B"-
~("t.registers.ff[5]._clk_B")->"t.registers.ff[5].__clk_B"+
~"t.registers.ff[5].d"&~"t.registers.ff[5]._clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5].__clk_B"&~"t.registers.ff[5]._mqi"->"t.registers.ff[5]._mqib"+
("t.registers.ff[5].d"&"t.registers.ff[5].__clk_B"|"t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._mqib"-
"t.registers.ff[5]._mqib"->"t.registers.ff[5]._mqi"-
~("t.registers.ff[5]._mqib")->"t.registers.ff[5]._mqi"+
~"t.registers.ff[5]._mqi"&~"t.registers.ff[5].__clk_B"|~"t.registers.ff[5].reset_B"|~"t.registers.ff[5]._sqi"&~"t.registers.ff[5]._clk_B"->"t.registers.ff[5]._sqib"+
("t.registers.ff[5]._mqi"&"t.registers.ff[5]._clk_B"|"t.registers.ff[5]._sqi"&"t.registers.ff[5].__clk_B")&"t.registers.ff[5].reset_B"->"t.registers.ff[5]._sqib"-
"t.registers.ff[5]._sqib"->"t.registers.ff[5]._sqi"-
~("t.registers.ff[5]._sqib")->"t.registers.ff[5]._sqi"+
"t.registers.ff[5]._sqib"->"t.registers.ff[5].q"-
~("t.registers.ff[5]._sqib")->"t.registers.ff[5].q"+
"t.registers.ff[6].clk_B"->"t.registers.ff[6]._clk_B"-
~("t.registers.ff[6].clk_B")->"t.registers.ff[6]._clk_B"+
"t.registers.ff[6]._clk_B"->"t.registers.ff[6].__clk_B"-
~("t.registers.ff[6]._clk_B")->"t.registers.ff[6].__clk_B"+
~"t.registers.ff[6].d"&~"t.registers.ff[6]._clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6].__clk_B"&~"t.registers.ff[6]._mqi"->"t.registers.ff[6]._mqib"+
("t.registers.ff[6].d"&"t.registers.ff[6].__clk_B"|"t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._mqib"-
"t.registers.ff[6]._mqib"->"t.registers.ff[6]._mqi"-
~("t.registers.ff[6]._mqib")->"t.registers.ff[6]._mqi"+
~"t.registers.ff[6]._mqi"&~"t.registers.ff[6].__clk_B"|~"t.registers.ff[6].reset_B"|~"t.registers.ff[6]._sqi"&~"t.registers.ff[6]._clk_B"->"t.registers.ff[6]._sqib"+
("t.registers.ff[6]._mqi"&"t.registers.ff[6]._clk_B"|"t.registers.ff[6]._sqi"&"t.registers.ff[6].__clk_B")&"t.registers.ff[6].reset_B"->"t.registers.ff[6]._sqib"-
"t.registers.ff[6]._sqib"->"t.registers.ff[6]._sqi"-
~("t.registers.ff[6]._sqib")->"t.registers.ff[6]._sqi"+
"t.registers.ff[6]._sqib"->"t.registers.ff[6].q"-
~("t.registers.ff[6]._sqib")->"t.registers.ff[6].q"+
"t.registers.ff[7].clk_B"->"t.registers.ff[7]._clk_B"-
~("t.registers.ff[7].clk_B")->"t.registers.ff[7]._clk_B"+
"t.registers.ff[7]._clk_B"->"t.registers.ff[7].__clk_B"-
~("t.registers.ff[7]._clk_B")->"t.registers.ff[7].__clk_B"+
~"t.registers.ff[7].d"&~"t.registers.ff[7]._clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7].__clk_B"&~"t.registers.ff[7]._mqi"->"t.registers.ff[7]._mqib"+
("t.registers.ff[7].d"&"t.registers.ff[7].__clk_B"|"t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._mqib"-
"t.registers.ff[7]._mqib"->"t.registers.ff[7]._mqi"-
~("t.registers.ff[7]._mqib")->"t.registers.ff[7]._mqi"+
~"t.registers.ff[7]._mqi"&~"t.registers.ff[7].__clk_B"|~"t.registers.ff[7].reset_B"|~"t.registers.ff[7]._sqi"&~"t.registers.ff[7]._clk_B"->"t.registers.ff[7]._sqib"+
("t.registers.ff[7]._mqi"&"t.registers.ff[7]._clk_B"|"t.registers.ff[7]._sqi"&"t.registers.ff[7].__clk_B")&"t.registers.ff[7].reset_B"->"t.registers.ff[7]._sqib"-
"t.registers.ff[7]._sqib"->"t.registers.ff[7]._sqi"-
~("t.registers.ff[7]._sqib")->"t.registers.ff[7]._sqi"+
"t.registers.ff[7]._sqib"->"t.registers.ff[7].q"-
~("t.registers.ff[7]._sqib")->"t.registers.ff[7].q"+
= "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[1]"
= "t.registers.ff[7].clk_B" "t.registers.clock_buffer[3].out[0]"
= "t.registers.ff[7].clk_B" "t.registers.ff[6].clk_B"
= "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[1]"
= "t.registers.ff[5].clk_B" "t.registers.clock_buffer[2].out[0]"
= "t.registers.ff[5].clk_B" "t.registers.ff[4].clk_B"
= "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[1]"
= "t.registers.ff[3].clk_B" "t.registers.clock_buffer[1].out[0]"
= "t.registers.ff[3].clk_B" "t.registers.ff[2].clk_B"
= "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[1]"
= "t.registers.ff[1].clk_B" "t.registers.clock_buffer[0].out[0]"
= "t.registers.ff[1].clk_B" "t.registers.ff[0].clk_B"
= "t.registers._clock_temp_inv" "t.registers.clk_X.in"
= "t.registers._clock_temp_inv" "t.registers.inv_clk.y"
= "t.registers.reset_mem_B" "t.registers.reset_buf_BXX.a"
"t.registers.clk_X.buf1.a"->"t.registers.clk_X.buf1._y"-
~("t.registers.clk_X.buf1.a")->"t.registers.clk_X.buf1._y"+
"t.registers.clk_X.buf1._y"->"t.registers.clk_X.buf1.y"-
~("t.registers.clk_X.buf1._y")->"t.registers.clk_X.buf1.y"+
= "t.registers.clk_X.supply.vdd" "t.registers.clk_X.buf1.vdd"
= "t.registers.clk_X.supply.vss" "t.registers.clk_X.buf1.vss"
= "t.registers.clk_X.out" "t.registers.clk_X.buf1.y"
= "t.registers.clk_X.in" "t.registers.clk_X.buf1.a"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
= "t.registers.in.a" "t.registers.ack_input_X.out"
= "t.registers.in.v" "t.registers.val_input_X.out"
= "t.registers.in.d.d[0].f" "t.registers._in_temp.d[0].f"
= "t.registers.in.d.d[0].t" "t.registers._in_temp.d[0].t"
= "t.registers.in.d.d[0].d[0]" "t.registers._in_temp.d[0].d[0]"
= "t.registers.in.d.d[0].d[1]" "t.registers._in_temp.d[0].d[1]"
= "t.registers.in.d.d[1].f" "t.registers._in_temp.d[1].f"
= "t.registers.in.d.d[1].t" "t.registers._in_temp.d[1].t"
= "t.registers.in.d.d[1].d[0]" "t.registers._in_temp.d[1].d[0]"
= "t.registers.in.d.d[1].d[1]" "t.registers._in_temp.d[1].d[1]"
= "t.registers.in.d.d[2].f" "t.registers._in_temp.d[2].f"
= "t.registers.in.d.d[2].t" "t.registers._in_temp.d[2].t"
= "t.registers.in.d.d[2].d[0]" "t.registers._in_temp.d[2].d[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers._in_temp.d[2].d[1]"
= "t.registers.in.d.d[3].f" "t.registers._in_temp.d[3].f"
= "t.registers.in.d.d[3].t" "t.registers._in_temp.d[3].t"
= "t.registers.in.d.d[3].d[0]" "t.registers._in_temp.d[3].d[0]"
= "t.registers.in.d.d[3].d[1]" "t.registers._in_temp.d[3].d[1]"
= "t.registers.in.d.d[4].f" "t.registers._in_temp.d[4].f"
= "t.registers.in.d.d[4].t" "t.registers._in_temp.d[4].t"
= "t.registers.in.d.d[4].d[0]" "t.registers._in_temp.d[4].d[0]"
= "t.registers.in.d.d[4].d[1]" "t.registers._in_temp.d[4].d[1]"
= "t.registers.in.d.d[4].d[0]" "t.registers.in.d.d[4].f"
= "t.registers.in.d.d[4].d[1]" "t.registers.in.d.d[4].t"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[1].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.atree[0].in[1]"
= "t.registers.in.d.d[3].d[0]" "t.registers.in.d.d[3].f"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[3].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.atree[2].in[1]"
= "t.registers.in.d.d[3].d[1]" "t.registers.in.d.d[3].t"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[2].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.atree[0].in[0]"
= "t.registers.in.d.d[2].d[0]" "t.registers.in.d.d[2].f"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[3].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.atree[1].in[0]"
= "t.registers.in.d.d[2].d[1]" "t.registers.in.d.d[2].t"
= "t.registers.in.d.d[1].d[0]" "t.registers.in.d.d[1].f"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[7].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[5].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[3].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.ff[1].d"
= "t.registers.in.d.d[1].d[1]" "t.registers.in.d.d[1].t"
= "t.registers.in.d.d[0].d[0]" "t.registers.in.d.d[0].f"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[6].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[4].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[2].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.ff[0].d"
= "t.registers.in.d.d[0].d[1]" "t.registers.in.d.d[0].t"
"t.registers.reset_buf_BX.a"->"t.registers.reset_buf_BX._y"-
~("t.registers.reset_buf_BX.a")->"t.registers.reset_buf_BX._y"+
"t.registers.reset_buf_BX._y"->"t.registers.reset_buf_BX.y"-
~("t.registers.reset_buf_BX._y")->"t.registers.reset_buf_BX.y"+
"t.registers.ack_dly.and2[0].a"&"t.registers.ack_dly.and2[0].b"->"t.registers.ack_dly.and2[0]._y"-
~("t.registers.ack_dly.and2[0].a"&"t.registers.ack_dly.and2[0].b")->"t.registers.ack_dly.and2[0]._y"+
"t.registers.ack_dly.and2[0]._y"->"t.registers.ack_dly.and2[0].y"-
~("t.registers.ack_dly.and2[0]._y")->"t.registers.ack_dly.and2[0].y"+
"t.registers.ack_dly.and2[1].a"&"t.registers.ack_dly.and2[1].b"->"t.registers.ack_dly.and2[1]._y"-
~("t.registers.ack_dly.and2[1].a"&"t.registers.ack_dly.and2[1].b")->"t.registers.ack_dly.and2[1]._y"+
"t.registers.ack_dly.and2[1]._y"->"t.registers.ack_dly.and2[1].y"-
~("t.registers.ack_dly.and2[1]._y")->"t.registers.ack_dly.and2[1].y"+
= "t.registers.ack_dly.s[0]" "t.registers.ack_dly.mu2[0].s"
= "t.registers.ack_dly.s[0]" "t.registers.ack_dly.and2[0].b"
= "t.registers.ack_dly.s[1]" "t.registers.ack_dly.mu2[1].s"
= "t.registers.ack_dly.s[1]" "t.registers.ack_dly.and2[1].b"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.dly[2].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.dly[1].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.dly[0].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.mu2[1].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.mu2[0].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.and2[1].vdd"
= "t.registers.ack_dly.supply.vdd" "t.registers.ack_dly.and2[0].vdd"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.dly[2].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.dly[1].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.dly[0].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.mu2[1].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.mu2[0].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.and2[1].vss"
= "t.registers.ack_dly.supply.vss" "t.registers.ack_dly.and2[0].vss"
"t.registers.ack_dly.mu2[0].s"->"t.registers.ack_dly.mu2[0]._s"-
~("t.registers.ack_dly.mu2[0].s")->"t.registers.ack_dly.mu2[0]._s"+
~"t.registers.ack_dly.mu2[0].a"&~"t.registers.ack_dly.mu2[0].s"|~"t.registers.ack_dly.mu2[0].b"&~"t.registers.ack_dly.mu2[0]._s"->"t.registers.ack_dly.mu2[0]._y"+
"t.registers.ack_dly.mu2[0].a"&"t.registers.ack_dly.mu2[0]._s"|"t.registers.ack_dly.mu2[0].b"&"t.registers.ack_dly.mu2[0].s"->"t.registers.ack_dly.mu2[0]._y"-
"t.registers.ack_dly.mu2[0]._y"->"t.registers.ack_dly.mu2[0].y"-
~("t.registers.ack_dly.mu2[0]._y")->"t.registers.ack_dly.mu2[0].y"+
"t.registers.ack_dly.mu2[1].s"->"t.registers.ack_dly.mu2[1]._s"-
~("t.registers.ack_dly.mu2[1].s")->"t.registers.ack_dly.mu2[1]._s"+
~"t.registers.ack_dly.mu2[1].a"&~"t.registers.ack_dly.mu2[1].s"|~"t.registers.ack_dly.mu2[1].b"&~"t.registers.ack_dly.mu2[1]._s"->"t.registers.ack_dly.mu2[1]._y"+
"t.registers.ack_dly.mu2[1].a"&"t.registers.ack_dly.mu2[1]._s"|"t.registers.ack_dly.mu2[1].b"&"t.registers.ack_dly.mu2[1].s"->"t.registers.ack_dly.mu2[1]._y"-
"t.registers.ack_dly.mu2[1]._y"->"t.registers.ack_dly.mu2[1].y"-
~("t.registers.ack_dly.mu2[1]._y")->"t.registers.ack_dly.mu2[1].y"+
"t.registers.ack_dly.dly[0].a"->"t.registers.ack_dly.dly[0]._y"-
~("t.registers.ack_dly.dly[0].a")->"t.registers.ack_dly.dly[0]._y"+
"t.registers.ack_dly.dly[0]._y"->"t.registers.ack_dly.dly[0].__y"-
~("t.registers.ack_dly.dly[0]._y")->"t.registers.ack_dly.dly[0].__y"+
"t.registers.ack_dly.dly[0].__y"->"t.registers.ack_dly.dly[0].___y"-
~("t.registers.ack_dly.dly[0].__y")->"t.registers.ack_dly.dly[0].___y"+
"t.registers.ack_dly.dly[0].___y"->"t.registers.ack_dly.dly[0].y"-
~("t.registers.ack_dly.dly[0].___y")->"t.registers.ack_dly.dly[0].y"+
"t.registers.ack_dly.dly[1].a"->"t.registers.ack_dly.dly[1]._y"-
~("t.registers.ack_dly.dly[1].a")->"t.registers.ack_dly.dly[1]._y"+
"t.registers.ack_dly.dly[1]._y"->"t.registers.ack_dly.dly[1].__y"-
~("t.registers.ack_dly.dly[1]._y")->"t.registers.ack_dly.dly[1].__y"+
"t.registers.ack_dly.dly[1].__y"->"t.registers.ack_dly.dly[1].___y"-
~("t.registers.ack_dly.dly[1].__y")->"t.registers.ack_dly.dly[1].___y"+
"t.registers.ack_dly.dly[1].___y"->"t.registers.ack_dly.dly[1].y"-
~("t.registers.ack_dly.dly[1].___y")->"t.registers.ack_dly.dly[1].y"+
"t.registers.ack_dly.dly[2].a"->"t.registers.ack_dly.dly[2]._y"-
~("t.registers.ack_dly.dly[2].a")->"t.registers.ack_dly.dly[2]._y"+
"t.registers.ack_dly.dly[2]._y"->"t.registers.ack_dly.dly[2].__y"-
~("t.registers.ack_dly.dly[2]._y")->"t.registers.ack_dly.dly[2].__y"+
"t.registers.ack_dly.dly[2].__y"->"t.registers.ack_dly.dly[2].___y"-
~("t.registers.ack_dly.dly[2].__y")->"t.registers.ack_dly.dly[2].___y"+
"t.registers.ack_dly.dly[2].___y"->"t.registers.ack_dly.dly[2].y"-
~("t.registers.ack_dly.dly[2].___y")->"t.registers.ack_dly.dly[2].y"+
= "t.registers.ack_dly.dly[2].y" "t.registers.ack_dly.mu2[1].b"
= "t.registers.ack_dly.dly[2].a" "t.registers.ack_dly.dly[1].y"
= "t.registers.ack_dly.dly[1].a" "t.registers.ack_dly.and2[1].y"
= "t.registers.ack_dly.dly[0].y" "t.registers.ack_dly.mu2[0].b"
= "t.registers.ack_dly.dly[0].a" "t.registers.ack_dly.and2[0].y"
= "t.registers.ack_dly._a[1]" "t.registers.ack_dly.mu2[1].a"
= "t.registers.ack_dly._a[1]" "t.registers.ack_dly.and2[1].a"
= "t.registers.ack_dly._a[1]" "t.registers.ack_dly.mu2[0].y"
= "t.registers.ack_dly.out" "t.registers.ack_dly.mu2[1].y"
= "t.registers.ack_dly.out" "t.registers.ack_dly._a[2]"
= "t.registers.ack_dly.in" "t.registers.ack_dly.mu2[0].a"
= "t.registers.ack_dly.in" "t.registers.ack_dly.and2[0].a"
= "t.registers.ack_dly.in" "t.registers.ack_dly._a[0]"
= "t.registers.reset_B" "t.registers.reset_buf_BX.a"
= "t.registers._reset_BX" "t.registers.reset_buf_BX.y"
= "t.registers._reset_mem_BXX[0]" "t.registers.reset_bufarray.out[0]"
= "t.registers._reset_mem_BXX[1]" "t.registers.reset_bufarray.out[1]"
= "t.registers._reset_mem_BXX[2]" "t.registers.reset_bufarray.out[2]"
= "t.registers._reset_mem_BXX[3]" "t.registers.reset_bufarray.out[3]"
= "t.registers._reset_mem_BXX[4]" "t.registers.reset_bufarray.out[4]"
= "t.registers._reset_mem_BXX[5]" "t.registers.reset_bufarray.out[5]"
= "t.registers._reset_mem_BXX[6]" "t.registers.reset_bufarray.out[6]"
= "t.registers._reset_mem_BXX[7]" "t.registers.reset_bufarray.out[7]"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[7].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[6].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[5].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[4].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[3].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[2].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[1].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers.ff[0].reset_B"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[7]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[6]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[5]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[4]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[3]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[2]"
= "t.registers._reset_mem_BXX[0]" "t.registers._reset_mem_BXX[1]"
= "t.registers._out_encoder[0]" "t.registers.and_encoder[0].a"
= "t.registers._out_encoder[0]" "t.registers.atree[0].out"
= "t.registers._out_encoder[1]" "t.registers.and_encoder[1].a"
= "t.registers._out_encoder[1]" "t.registers.atree[1].out"
= "t.registers._out_encoder[2]" "t.registers.and_encoder[2].a"
= "t.registers._out_encoder[2]" "t.registers.atree[2].out"
= "t.registers._out_encoder[3]" "t.registers.and_encoder[3].a"
= "t.registers._out_encoder[3]" "t.registers.atree[3].out"
= "t.registers._clock_word_temp[0]" "t.registers.clock_buffer[0].in"
= "t.registers._clock_word_temp[0]" "t.registers.and_encoder[0].y"
= "t.registers._clock_word_temp[1]" "t.registers.clock_buffer[1].in"
= "t.registers._clock_word_temp[1]" "t.registers.and_encoder[1].y"
= "t.registers._clock_word_temp[2]" "t.registers.clock_buffer[2].in"
= "t.registers._clock_word_temp[2]" "t.registers.and_encoder[2].y"
= "t.registers._clock_word_temp[3]" "t.registers.clock_buffer[3].in"
= "t.registers._clock_word_temp[3]" "t.registers.and_encoder[3].y"
"t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b"->"t.registers.and_encoder[0]._y"-
~("t.registers.and_encoder[0].a"&"t.registers.and_encoder[0].b")->"t.registers.and_encoder[0]._y"+
"t.registers.and_encoder[0]._y"->"t.registers.and_encoder[0].y"-
~("t.registers.and_encoder[0]._y")->"t.registers.and_encoder[0].y"+
"t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b"->"t.registers.and_encoder[1]._y"-
~("t.registers.and_encoder[1].a"&"t.registers.and_encoder[1].b")->"t.registers.and_encoder[1]._y"+
"t.registers.and_encoder[1]._y"->"t.registers.and_encoder[1].y"-
~("t.registers.and_encoder[1]._y")->"t.registers.and_encoder[1].y"+
"t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b"->"t.registers.and_encoder[2]._y"-
~("t.registers.and_encoder[2].a"&"t.registers.and_encoder[2].b")->"t.registers.and_encoder[2]._y"+
"t.registers.and_encoder[2]._y"->"t.registers.and_encoder[2].y"-
~("t.registers.and_encoder[2]._y")->"t.registers.and_encoder[2].y"+
"t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b"->"t.registers.and_encoder[3]._y"-
~("t.registers.and_encoder[3].a"&"t.registers.and_encoder[3].b")->"t.registers.and_encoder[3]._y"+
"t.registers.and_encoder[3]._y"->"t.registers.and_encoder[3].y"-
~("t.registers.and_encoder[3]._y")->"t.registers.and_encoder[3].y"+
= "t.registers._in_temp.d[0].d[0]" "t.registers._in_temp.d[0].f"
= "t.registers._in_temp.d[0].d[1]" "t.registers._in_temp.d[0].t"
= "t.registers._in_temp.d[1].d[0]" "t.registers._in_temp.d[1].f"
= "t.registers._in_temp.d[1].d[1]" "t.registers._in_temp.d[1].t"
= "t.registers._in_temp.d[2].d[0]" "t.registers._in_temp.d[2].f"
= "t.registers._in_temp.d[2].d[1]" "t.registers._in_temp.d[2].t"
= "t.registers._in_temp.d[3].d[0]" "t.registers._in_temp.d[3].f"
= "t.registers._in_temp.d[3].d[1]" "t.registers._in_temp.d[3].t"
= "t.registers._in_temp.d[4].d[0]" "t.registers._in_temp.d[4].f"
= "t.registers._in_temp.d[4].d[1]" "t.registers._in_temp.d[4].t"
= "t.registers._in_temp.d[4].d[0]" "t.registers._in_temp.d[4].f"
= "t.registers._in_temp.d[4].d[1]" "t.registers._in_temp.d[4].t"
= "t.registers._in_temp.d[3].d[0]" "t.registers._in_temp.d[3].f"
= "t.registers._in_temp.d[3].d[1]" "t.registers._in_temp.d[3].t"
= "t.registers._in_temp.d[2].d[0]" "t.registers._in_temp.d[2].f"
= "t.registers._in_temp.d[2].d[1]" "t.registers._in_temp.d[2].t"
= "t.registers._in_temp.d[1].d[0]" "t.registers._in_temp.d[1].f"
= "t.registers._in_temp.d[1].d[1]" "t.registers._in_temp.d[1].t"
= "t.registers._in_temp.d[0].d[0]" "t.registers._in_temp.d[0].f"
= "t.registers._in_temp.d[0].d[1]" "t.registers._in_temp.d[0].t"
= "t.registers._in_temp.d[0].f" "t.registers.val_input.in.d[0].f"
= "t.registers._in_temp.d[0].t" "t.registers.val_input.in.d[0].t"
= "t.registers._in_temp.d[0].d[0]" "t.registers.val_input.in.d[0].d[0]"
= "t.registers._in_temp.d[0].d[1]" "t.registers.val_input.in.d[0].d[1]"
= "t.registers._in_temp.d[1].f" "t.registers.val_input.in.d[1].f"
= "t.registers._in_temp.d[1].t" "t.registers.val_input.in.d[1].t"
= "t.registers._in_temp.d[1].d[0]" "t.registers.val_input.in.d[1].d[0]"
= "t.registers._in_temp.d[1].d[1]" "t.registers.val_input.in.d[1].d[1]"
= "t.registers._in_temp.d[2].f" "t.registers.val_input.in.d[2].f"
= "t.registers._in_temp.d[2].t" "t.registers.val_input.in.d[2].t"
= "t.registers._in_temp.d[2].d[0]" "t.registers.val_input.in.d[2].d[0]"
= "t.registers._in_temp.d[2].d[1]" "t.registers.val_input.in.d[2].d[1]"
= "t.registers._in_temp.d[3].f" "t.registers.val_input.in.d[3].f"
= "t.registers._in_temp.d[3].t" "t.registers.val_input.in.d[3].t"
= "t.registers._in_temp.d[3].d[0]" "t.registers.val_input.in.d[3].d[0]"
= "t.registers._in_temp.d[3].d[1]" "t.registers.val_input.in.d[3].d[1]"
= "t.registers._in_temp.d[4].f" "t.registers.val_input.in.d[4].f"
= "t.registers._in_temp.d[4].t" "t.registers.val_input.in.d[4].t"
= "t.registers._in_temp.d[4].d[0]" "t.registers.val_input.in.d[4].d[0]"
= "t.registers._in_temp.d[4].d[1]" "t.registers.val_input.in.d[4].d[1]"
= "t.registers._reset_mem_BX" "t.registers.reset_bufarray.in"
= "t.registers._reset_mem_BX" "t.registers.reset_buf_BXX.y"
= "t.registers._in_a_temp" "t.registers.ack_input_X.in"
= "t.registers._in_a_temp" "t.registers.ack_dly.out"
= "t.registers.supply.vss" "t.registers.clock_buffer[3].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[3].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[2].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[2].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[1].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[1].supply.vdd"
= "t.registers.supply.vss" "t.registers.clock_buffer[0].supply.vss"
= "t.registers.supply.vdd" "t.registers.clock_buffer[0].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[3].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[3].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[2].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[2].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[1].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[1].supply.vdd"
= "t.registers.supply.vss" "t.registers.atree[0].supply.vss"
= "t.registers.supply.vdd" "t.registers.atree[0].supply.vdd"
= "t.registers.supply.vss" "t.registers.reset_bufarray.supply.vss"
= "t.registers.supply.vdd" "t.registers.reset_bufarray.supply.vdd"
= "t.registers.supply.vss" "t.registers.ack_input_X.supply.vss"
= "t.registers.supply.vdd" "t.registers.ack_input_X.supply.vdd"
= "t.registers.supply.vss" "t.registers.ack_dly.supply.vss"
= "t.registers.supply.vdd" "t.registers.ack_dly.supply.vdd"
= "t.registers.supply.vss" "t.registers.clk_X.supply.vss"
= "t.registers.supply.vdd" "t.registers.clk_X.supply.vdd"
= "t.registers.supply.vss" "t.registers.clk_dly.supply.vss"
= "t.registers.supply.vdd" "t.registers.clk_dly.supply.vdd"
= "t.registers.supply.vss" "t.registers.val_input_X.supply.vss"
= "t.registers.supply.vdd" "t.registers.val_input_X.supply.vdd"
= "t.registers.supply.vss" "t.registers.val_input.supply.vss"
= "t.registers.supply.vdd" "t.registers.val_input.supply.vdd"
= "t.registers.supply.vdd" "t.registers.ff[7].vdd"
= "t.registers.supply.vdd" "t.registers.ff[6].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[3].vdd"
= "t.registers.supply.vdd" "t.registers.ff[5].vdd"
= "t.registers.supply.vdd" "t.registers.ff[4].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[2].vdd"
= "t.registers.supply.vdd" "t.registers.ff[3].vdd"
= "t.registers.supply.vdd" "t.registers.ff[2].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[1].vdd"
= "t.registers.supply.vdd" "t.registers.ff[1].vdd"
= "t.registers.supply.vdd" "t.registers.ff[0].vdd"
= "t.registers.supply.vdd" "t.registers.and_encoder[0].vdd"
= "t.registers.supply.vdd" "t.registers.reset_buf_BXX.vdd"
= "t.registers.supply.vdd" "t.registers.reset_buf_BX.vdd"
= "t.registers.supply.vdd" "t.registers.inv_clk.vdd"
= "t.registers.supply.vss" "t.registers.ff[7].vss"
= "t.registers.supply.vss" "t.registers.ff[6].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[3].vss"
= "t.registers.supply.vss" "t.registers.ff[5].vss"
= "t.registers.supply.vss" "t.registers.ff[4].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[2].vss"
= "t.registers.supply.vss" "t.registers.ff[3].vss"
= "t.registers.supply.vss" "t.registers.ff[2].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[1].vss"
= "t.registers.supply.vss" "t.registers.ff[1].vss"
= "t.registers.supply.vss" "t.registers.ff[0].vss"
= "t.registers.supply.vss" "t.registers.and_encoder[0].vss"
= "t.registers.supply.vss" "t.registers.reset_buf_BXX.vss"
= "t.registers.supply.vss" "t.registers.reset_buf_BX.vss"
= "t.registers.supply.vss" "t.registers.inv_clk.vss"
= "t.registers.dly_cfg[0]" "t.registers.ack_dly.s[0]"
= "t.registers.dly_cfg[1]" "t.registers.ack_dly.s[1]"
= "t.registers.dly_cfg[0]" "t.registers.clk_dly.s[0]"
= "t.registers.dly_cfg[1]" "t.registers.clk_dly.s[1]"
"t.registers.inv_clk.a"->"t.registers.inv_clk.y"-
~("t.registers.inv_clk.a")->"t.registers.inv_clk.y"+
= "t.registers.data[3].d[0]" "t.registers.ff[6].q"
= "t.registers.data[3].d[1]" "t.registers.ff[7].q"
= "t.registers.data[2].d[0]" "t.registers.ff[4].q"
= "t.registers.data[2].d[1]" "t.registers.ff[5].q"
= "t.registers.data[1].d[0]" "t.registers.ff[2].q"
= "t.registers.data[1].d[1]" "t.registers.ff[3].q"
= "t.registers.data[0].d[0]" "t.registers.ff[0].q"
= "t.registers.data[0].d[1]" "t.registers.ff[1].q"
"t.registers.val_input_X.buf1.a"->"t.registers.val_input_X.buf1._y"-
~("t.registers.val_input_X.buf1.a")->"t.registers.val_input_X.buf1._y"+
"t.registers.val_input_X.buf1._y"->"t.registers.val_input_X.buf1.y"-
~("t.registers.val_input_X.buf1._y")->"t.registers.val_input_X.buf1.y"+
= "t.registers.val_input_X.supply.vdd" "t.registers.val_input_X.buf1.vdd"
= "t.registers.val_input_X.supply.vss" "t.registers.val_input_X.buf1.vss"
= "t.registers.val_input_X.out" "t.registers.val_input_X.buf1.y"
= "t.registers.val_input_X.in" "t.registers.val_input_X.buf1.a"
"t.registers.ack_input_X.buf1.a"->"t.registers.ack_input_X.buf1._y"-
~("t.registers.ack_input_X.buf1.a")->"t.registers.ack_input_X.buf1._y"+
"t.registers.ack_input_X.buf1._y"->"t.registers.ack_input_X.buf1.y"-
~("t.registers.ack_input_X.buf1._y")->"t.registers.ack_input_X.buf1.y"+
= "t.registers.ack_input_X.supply.vdd" "t.registers.ack_input_X.buf1.vdd"
= "t.registers.ack_input_X.supply.vss" "t.registers.ack_input_X.buf1.vss"
= "t.registers.ack_input_X.out" "t.registers.ack_input_X.buf1.y"
= "t.registers.ack_input_X.in" "t.registers.ack_input_X.buf1.a"
= "t.registers.atree[0].supply.vdd" "t.registers.atree[0].and2s[0].vdd"
= "t.registers.atree[0].supply.vss" "t.registers.atree[0].and2s[0].vss"
"t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b"->"t.registers.atree[0].and2s[0]._y"-
~("t.registers.atree[0].and2s[0].a"&"t.registers.atree[0].and2s[0].b")->"t.registers.atree[0].and2s[0]._y"+
"t.registers.atree[0].and2s[0]._y"->"t.registers.atree[0].and2s[0].y"-
~("t.registers.atree[0].and2s[0]._y")->"t.registers.atree[0].and2s[0].y"+
= "t.registers.atree[0].in[0]" "t.registers.atree[0].and2s[0].a"
= "t.registers.atree[0].in[0]" "t.registers.atree[0].tmp[0]"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].and2s[0].b"
= "t.registers.atree[0].in[1]" "t.registers.atree[0].tmp[1]"
= "t.registers.atree[0].out" "t.registers.atree[0].and2s[0].y"
= "t.registers.atree[0].out" "t.registers.atree[0].tmp[2]"
= "t.registers.atree[1].supply.vdd" "t.registers.atree[1].and2s[0].vdd"
= "t.registers.atree[1].supply.vss" "t.registers.atree[1].and2s[0].vss"
"t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b"->"t.registers.atree[1].and2s[0]._y"-
~("t.registers.atree[1].and2s[0].a"&"t.registers.atree[1].and2s[0].b")->"t.registers.atree[1].and2s[0]._y"+
"t.registers.atree[1].and2s[0]._y"->"t.registers.atree[1].and2s[0].y"-
~("t.registers.atree[1].and2s[0]._y")->"t.registers.atree[1].and2s[0].y"+
= "t.registers.atree[1].in[0]" "t.registers.atree[1].and2s[0].a"
= "t.registers.atree[1].in[0]" "t.registers.atree[1].tmp[0]"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].and2s[0].b"
= "t.registers.atree[1].in[1]" "t.registers.atree[1].tmp[1]"
= "t.registers.atree[1].out" "t.registers.atree[1].and2s[0].y"
= "t.registers.atree[1].out" "t.registers.atree[1].tmp[2]"
= "t.registers.atree[2].supply.vdd" "t.registers.atree[2].and2s[0].vdd"
= "t.registers.atree[2].supply.vss" "t.registers.atree[2].and2s[0].vss"
"t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b"->"t.registers.atree[2].and2s[0]._y"-
~("t.registers.atree[2].and2s[0].a"&"t.registers.atree[2].and2s[0].b")->"t.registers.atree[2].and2s[0]._y"+
"t.registers.atree[2].and2s[0]._y"->"t.registers.atree[2].and2s[0].y"-
~("t.registers.atree[2].and2s[0]._y")->"t.registers.atree[2].and2s[0].y"+
= "t.registers.atree[2].in[0]" "t.registers.atree[2].and2s[0].a"
= "t.registers.atree[2].in[0]" "t.registers.atree[2].tmp[0]"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].and2s[0].b"
= "t.registers.atree[2].in[1]" "t.registers.atree[2].tmp[1]"
= "t.registers.atree[2].out" "t.registers.atree[2].and2s[0].y"
= "t.registers.atree[2].out" "t.registers.atree[2].tmp[2]"
= "t.registers.atree[3].supply.vdd" "t.registers.atree[3].and2s[0].vdd"
= "t.registers.atree[3].supply.vss" "t.registers.atree[3].and2s[0].vss"
"t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b"->"t.registers.atree[3].and2s[0]._y"-
~("t.registers.atree[3].and2s[0].a"&"t.registers.atree[3].and2s[0].b")->"t.registers.atree[3].and2s[0]._y"+
"t.registers.atree[3].and2s[0]._y"->"t.registers.atree[3].and2s[0].y"-
~("t.registers.atree[3].and2s[0]._y")->"t.registers.atree[3].and2s[0].y"+
= "t.registers.atree[3].in[0]" "t.registers.atree[3].and2s[0].a"
= "t.registers.atree[3].in[0]" "t.registers.atree[3].tmp[0]"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].and2s[0].b"
= "t.registers.atree[3].in[1]" "t.registers.atree[3].tmp[1]"
= "t.registers.atree[3].out" "t.registers.atree[3].and2s[0].y"
= "t.registers.atree[3].out" "t.registers.atree[3].tmp[2]"
~"t.registers.val_input.ct.C2Els[0].c1"&~"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"+
"t.registers.val_input.ct.C2Els[0].c1"&"t.registers.val_input.ct.C2Els[0].c2"->"t.registers.val_input.ct.C2Els[0]._y"-
"t.registers.val_input.ct.C2Els[0]._y"->"t.registers.val_input.ct.C2Els[0].y"-
~("t.registers.val_input.ct.C2Els[0]._y")->"t.registers.val_input.ct.C2Els[0].y"+
~"t.registers.val_input.ct.C2Els[1].c1"&~"t.registers.val_input.ct.C2Els[1].c2"->"t.registers.val_input.ct.C2Els[1]._y"+
"t.registers.val_input.ct.C2Els[1].c1"&"t.registers.val_input.ct.C2Els[1].c2"->"t.registers.val_input.ct.C2Els[1]._y"-
"t.registers.val_input.ct.C2Els[1]._y"->"t.registers.val_input.ct.C2Els[1].y"-
~("t.registers.val_input.ct.C2Els[1]._y")->"t.registers.val_input.ct.C2Els[1].y"+
~"t.registers.val_input.ct.C3Els[0].c1"&~"t.registers.val_input.ct.C3Els[0].c2"&~"t.registers.val_input.ct.C3Els[0].c3"->"t.registers.val_input.ct.C3Els[0]._y"+
"t.registers.val_input.ct.C3Els[0].c1"&"t.registers.val_input.ct.C3Els[0].c2"&"t.registers.val_input.ct.C3Els[0].c3"->"t.registers.val_input.ct.C3Els[0]._y"-
"t.registers.val_input.ct.C3Els[0]._y"->"t.registers.val_input.ct.C3Els[0].y"-
~("t.registers.val_input.ct.C3Els[0]._y")->"t.registers.val_input.ct.C3Els[0].y"+
= "t.registers.val_input.ct.tmp[5]" "t.registers.val_input.ct.C2Els[1].c1"
= "t.registers.val_input.ct.tmp[5]" "t.registers.val_input.ct.C2Els[0].y"
= "t.registers.val_input.ct.tmp[6]" "t.registers.val_input.ct.C2Els[1].c2"
= "t.registers.val_input.ct.tmp[6]" "t.registers.val_input.ct.C3Els[0].y"
= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C3Els[0].vdd"
= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C2Els[1].vdd"
= "t.registers.val_input.ct.supply.vdd" "t.registers.val_input.ct.C2Els[0].vdd"
= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C3Els[0].vss"
= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C2Els[1].vss"
= "t.registers.val_input.ct.supply.vss" "t.registers.val_input.ct.C2Els[0].vss"
= "t.registers.val_input.ct.in[0]" "t.registers.val_input.ct.C2Els[0].c1"
= "t.registers.val_input.ct.in[0]" "t.registers.val_input.ct.tmp[0]"
= "t.registers.val_input.ct.in[1]" "t.registers.val_input.ct.C2Els[0].c2"
= "t.registers.val_input.ct.in[1]" "t.registers.val_input.ct.tmp[1]"
= "t.registers.val_input.ct.in[2]" "t.registers.val_input.ct.C3Els[0].c1"
= "t.registers.val_input.ct.in[2]" "t.registers.val_input.ct.tmp[2]"
= "t.registers.val_input.ct.in[3]" "t.registers.val_input.ct.C3Els[0].c2"
= "t.registers.val_input.ct.in[3]" "t.registers.val_input.ct.tmp[3]"
= "t.registers.val_input.ct.in[4]" "t.registers.val_input.ct.C3Els[0].c3"
= "t.registers.val_input.ct.in[4]" "t.registers.val_input.ct.tmp[4]"
= "t.registers.val_input.ct.out" "t.registers.val_input.ct.C2Els[1].y"
= "t.registers.val_input.ct.out" "t.registers.val_input.ct.tmp[7]"
= "t.registers.val_input.ct.in[0]" "t.registers.val_input.OR2_tf[0].y"
= "t.registers.val_input.ct.in[1]" "t.registers.val_input.OR2_tf[1].y"
= "t.registers.val_input.ct.in[2]" "t.registers.val_input.OR2_tf[2].y"
= "t.registers.val_input.ct.in[3]" "t.registers.val_input.OR2_tf[3].y"
= "t.registers.val_input.ct.in[4]" "t.registers.val_input.OR2_tf[4].y"
"t.registers.val_input.OR2_tf[0].a"|"t.registers.val_input.OR2_tf[0].b"->"t.registers.val_input.OR2_tf[0]._y"-
~("t.registers.val_input.OR2_tf[0].a"|"t.registers.val_input.OR2_tf[0].b")->"t.registers.val_input.OR2_tf[0]._y"+
"t.registers.val_input.OR2_tf[0]._y"->"t.registers.val_input.OR2_tf[0].y"-
~("t.registers.val_input.OR2_tf[0]._y")->"t.registers.val_input.OR2_tf[0].y"+
"t.registers.val_input.OR2_tf[1].a"|"t.registers.val_input.OR2_tf[1].b"->"t.registers.val_input.OR2_tf[1]._y"-
~("t.registers.val_input.OR2_tf[1].a"|"t.registers.val_input.OR2_tf[1].b")->"t.registers.val_input.OR2_tf[1]._y"+
"t.registers.val_input.OR2_tf[1]._y"->"t.registers.val_input.OR2_tf[1].y"-
~("t.registers.val_input.OR2_tf[1]._y")->"t.registers.val_input.OR2_tf[1].y"+
"t.registers.val_input.OR2_tf[2].a"|"t.registers.val_input.OR2_tf[2].b"->"t.registers.val_input.OR2_tf[2]._y"-
~("t.registers.val_input.OR2_tf[2].a"|"t.registers.val_input.OR2_tf[2].b")->"t.registers.val_input.OR2_tf[2]._y"+
"t.registers.val_input.OR2_tf[2]._y"->"t.registers.val_input.OR2_tf[2].y"-
~("t.registers.val_input.OR2_tf[2]._y")->"t.registers.val_input.OR2_tf[2].y"+
"t.registers.val_input.OR2_tf[3].a"|"t.registers.val_input.OR2_tf[3].b"->"t.registers.val_input.OR2_tf[3]._y"-
~("t.registers.val_input.OR2_tf[3].a"|"t.registers.val_input.OR2_tf[3].b")->"t.registers.val_input.OR2_tf[3]._y"+
"t.registers.val_input.OR2_tf[3]._y"->"t.registers.val_input.OR2_tf[3].y"-
~("t.registers.val_input.OR2_tf[3]._y")->"t.registers.val_input.OR2_tf[3].y"+
"t.registers.val_input.OR2_tf[4].a"|"t.registers.val_input.OR2_tf[4].b"->"t.registers.val_input.OR2_tf[4]._y"-
~("t.registers.val_input.OR2_tf[4].a"|"t.registers.val_input.OR2_tf[4].b")->"t.registers.val_input.OR2_tf[4]._y"+
"t.registers.val_input.OR2_tf[4]._y"->"t.registers.val_input.OR2_tf[4].y"-
~("t.registers.val_input.OR2_tf[4]._y")->"t.registers.val_input.OR2_tf[4].y"+
= "t.registers.val_input.supply.vss" "t.registers.val_input.ct.supply.vss"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.ct.supply.vdd"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[4].vdd"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[3].vdd"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[2].vdd"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[1].vdd"
= "t.registers.val_input.supply.vdd" "t.registers.val_input.OR2_tf[0].vdd"
= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[4].vss"
= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[3].vss"
= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[2].vss"
= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[1].vss"
= "t.registers.val_input.supply.vss" "t.registers.val_input.OR2_tf[0].vss"
= "t.registers.val_input.out" "t.registers.val_input.ct.out"
= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f"
= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t"
= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f"
= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t"
= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f"
= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t"
= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f"
= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t"
= "t.registers.val_input.in.d[4].d[0]" "t.registers.val_input.in.d[4].f"
= "t.registers.val_input.in.d[4].d[1]" "t.registers.val_input.in.d[4].t"
= "t.registers.val_input.in.d[4].d[0]" "t.registers.val_input.in.d[4].f"
= "t.registers.val_input.in.d[4].d[1]" "t.registers.val_input.in.d[4].t"
= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f"
= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t"
= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f"
= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t"
= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f"
= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t"
= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f"
= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t"
= "t.registers.val_input.in.d[4].d[0]" "t.registers.val_input.OR2_tf[4].b"
= "t.registers.val_input.in.d[4].d[0]" "t.registers.val_input.in.d[4].f"
= "t.registers.val_input.in.d[4].d[1]" "t.registers.val_input.OR2_tf[4].a"
= "t.registers.val_input.in.d[4].d[1]" "t.registers.val_input.in.d[4].t"
= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.OR2_tf[3].b"
= "t.registers.val_input.in.d[3].d[0]" "t.registers.val_input.in.d[3].f"
= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.OR2_tf[3].a"
= "t.registers.val_input.in.d[3].d[1]" "t.registers.val_input.in.d[3].t"
= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.OR2_tf[2].b"
= "t.registers.val_input.in.d[2].d[0]" "t.registers.val_input.in.d[2].f"
= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.OR2_tf[2].a"
= "t.registers.val_input.in.d[2].d[1]" "t.registers.val_input.in.d[2].t"
= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.OR2_tf[1].b"
= "t.registers.val_input.in.d[1].d[0]" "t.registers.val_input.in.d[1].f"
= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.OR2_tf[1].a"
= "t.registers.val_input.in.d[1].d[1]" "t.registers.val_input.in.d[1].t"
= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.OR2_tf[0].b"
= "t.registers.val_input.in.d[0].d[0]" "t.registers.val_input.in.d[0].f"
= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.OR2_tf[0].a"
= "t.registers.val_input.in.d[0].d[1]" "t.registers.val_input.in.d[0].t"
"t.registers.clk_dly.and2[0].a"&"t.registers.clk_dly.and2[0].b"->"t.registers.clk_dly.and2[0]._y"-
~("t.registers.clk_dly.and2[0].a"&"t.registers.clk_dly.and2[0].b")->"t.registers.clk_dly.and2[0]._y"+
"t.registers.clk_dly.and2[0]._y"->"t.registers.clk_dly.and2[0].y"-
~("t.registers.clk_dly.and2[0]._y")->"t.registers.clk_dly.and2[0].y"+
"t.registers.clk_dly.and2[1].a"&"t.registers.clk_dly.and2[1].b"->"t.registers.clk_dly.and2[1]._y"-
~("t.registers.clk_dly.and2[1].a"&"t.registers.clk_dly.and2[1].b")->"t.registers.clk_dly.and2[1]._y"+
"t.registers.clk_dly.and2[1]._y"->"t.registers.clk_dly.and2[1].y"-
~("t.registers.clk_dly.and2[1]._y")->"t.registers.clk_dly.and2[1].y"+
= "t.registers.clk_dly.s[0]" "t.registers.clk_dly.mu2[0].s"
= "t.registers.clk_dly.s[0]" "t.registers.clk_dly.and2[0].b"
= "t.registers.clk_dly.s[1]" "t.registers.clk_dly.mu2[1].s"
= "t.registers.clk_dly.s[1]" "t.registers.clk_dly.and2[1].b"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.dly[2].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.dly[1].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.dly[0].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.mu2[1].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.mu2[0].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.and2[1].vdd"
= "t.registers.clk_dly.supply.vdd" "t.registers.clk_dly.and2[0].vdd"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.dly[2].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.dly[1].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.dly[0].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.mu2[1].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.mu2[0].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.and2[1].vss"
= "t.registers.clk_dly.supply.vss" "t.registers.clk_dly.and2[0].vss"
"t.registers.clk_dly.mu2[0].s"->"t.registers.clk_dly.mu2[0]._s"-
~("t.registers.clk_dly.mu2[0].s")->"t.registers.clk_dly.mu2[0]._s"+
~"t.registers.clk_dly.mu2[0].a"&~"t.registers.clk_dly.mu2[0].s"|~"t.registers.clk_dly.mu2[0].b"&~"t.registers.clk_dly.mu2[0]._s"->"t.registers.clk_dly.mu2[0]._y"+
"t.registers.clk_dly.mu2[0].a"&"t.registers.clk_dly.mu2[0]._s"|"t.registers.clk_dly.mu2[0].b"&"t.registers.clk_dly.mu2[0].s"->"t.registers.clk_dly.mu2[0]._y"-
"t.registers.clk_dly.mu2[0]._y"->"t.registers.clk_dly.mu2[0].y"-
~("t.registers.clk_dly.mu2[0]._y")->"t.registers.clk_dly.mu2[0].y"+
"t.registers.clk_dly.mu2[1].s"->"t.registers.clk_dly.mu2[1]._s"-
~("t.registers.clk_dly.mu2[1].s")->"t.registers.clk_dly.mu2[1]._s"+
~"t.registers.clk_dly.mu2[1].a"&~"t.registers.clk_dly.mu2[1].s"|~"t.registers.clk_dly.mu2[1].b"&~"t.registers.clk_dly.mu2[1]._s"->"t.registers.clk_dly.mu2[1]._y"+
"t.registers.clk_dly.mu2[1].a"&"t.registers.clk_dly.mu2[1]._s"|"t.registers.clk_dly.mu2[1].b"&"t.registers.clk_dly.mu2[1].s"->"t.registers.clk_dly.mu2[1]._y"-
"t.registers.clk_dly.mu2[1]._y"->"t.registers.clk_dly.mu2[1].y"-
~("t.registers.clk_dly.mu2[1]._y")->"t.registers.clk_dly.mu2[1].y"+
"t.registers.clk_dly.dly[0].a"->"t.registers.clk_dly.dly[0]._y"-
~("t.registers.clk_dly.dly[0].a")->"t.registers.clk_dly.dly[0]._y"+
"t.registers.clk_dly.dly[0]._y"->"t.registers.clk_dly.dly[0].__y"-
~("t.registers.clk_dly.dly[0]._y")->"t.registers.clk_dly.dly[0].__y"+
"t.registers.clk_dly.dly[0].__y"->"t.registers.clk_dly.dly[0].___y"-
~("t.registers.clk_dly.dly[0].__y")->"t.registers.clk_dly.dly[0].___y"+
"t.registers.clk_dly.dly[0].___y"->"t.registers.clk_dly.dly[0].y"-
~("t.registers.clk_dly.dly[0].___y")->"t.registers.clk_dly.dly[0].y"+
"t.registers.clk_dly.dly[1].a"->"t.registers.clk_dly.dly[1]._y"-
~("t.registers.clk_dly.dly[1].a")->"t.registers.clk_dly.dly[1]._y"+
"t.registers.clk_dly.dly[1]._y"->"t.registers.clk_dly.dly[1].__y"-
~("t.registers.clk_dly.dly[1]._y")->"t.registers.clk_dly.dly[1].__y"+
"t.registers.clk_dly.dly[1].__y"->"t.registers.clk_dly.dly[1].___y"-
~("t.registers.clk_dly.dly[1].__y")->"t.registers.clk_dly.dly[1].___y"+
"t.registers.clk_dly.dly[1].___y"->"t.registers.clk_dly.dly[1].y"-
~("t.registers.clk_dly.dly[1].___y")->"t.registers.clk_dly.dly[1].y"+
"t.registers.clk_dly.dly[2].a"->"t.registers.clk_dly.dly[2]._y"-
~("t.registers.clk_dly.dly[2].a")->"t.registers.clk_dly.dly[2]._y"+
"t.registers.clk_dly.dly[2]._y"->"t.registers.clk_dly.dly[2].__y"-
~("t.registers.clk_dly.dly[2]._y")->"t.registers.clk_dly.dly[2].__y"+
"t.registers.clk_dly.dly[2].__y"->"t.registers.clk_dly.dly[2].___y"-
~("t.registers.clk_dly.dly[2].__y")->"t.registers.clk_dly.dly[2].___y"+
"t.registers.clk_dly.dly[2].___y"->"t.registers.clk_dly.dly[2].y"-
~("t.registers.clk_dly.dly[2].___y")->"t.registers.clk_dly.dly[2].y"+
= "t.registers.clk_dly.dly[2].y" "t.registers.clk_dly.mu2[1].b"
= "t.registers.clk_dly.dly[2].a" "t.registers.clk_dly.dly[1].y"
= "t.registers.clk_dly.dly[1].a" "t.registers.clk_dly.and2[1].y"
= "t.registers.clk_dly.dly[0].y" "t.registers.clk_dly.mu2[0].b"
= "t.registers.clk_dly.dly[0].a" "t.registers.clk_dly.and2[0].y"
= "t.registers.clk_dly._a[1]" "t.registers.clk_dly.mu2[1].a"
= "t.registers.clk_dly._a[1]" "t.registers.clk_dly.and2[1].a"
= "t.registers.clk_dly._a[1]" "t.registers.clk_dly.mu2[0].y"
= "t.registers.clk_dly.out" "t.registers.clk_dly.mu2[1].y"
= "t.registers.clk_dly.out" "t.registers.clk_dly._a[2]"
= "t.registers.clk_dly.in" "t.registers.clk_dly.mu2[0].a"
= "t.registers.clk_dly.in" "t.registers.clk_dly.and2[0].a"
= "t.registers.clk_dly.in" "t.registers.clk_dly._a[0]"
"t.registers.reset_buf_BXX.a"->"t.registers.reset_buf_BXX._y"-
~("t.registers.reset_buf_BXX.a")->"t.registers.reset_buf_BXX._y"+
"t.registers.reset_buf_BXX._y"->"t.registers.reset_buf_BXX.y"-
~("t.registers.reset_buf_BXX._y")->"t.registers.reset_buf_BXX.y"+
"t.registers.clock_buffer[0].buf1.a"->"t.registers.clock_buffer[0].buf1._y"-
~("t.registers.clock_buffer[0].buf1.a")->"t.registers.clock_buffer[0].buf1._y"+
"t.registers.clock_buffer[0].buf1._y"->"t.registers.clock_buffer[0].buf1.y"-
~("t.registers.clock_buffer[0].buf1._y")->"t.registers.clock_buffer[0].buf1.y"+
= "t.registers.clock_buffer[0].supply.vdd" "t.registers.clock_buffer[0].buf1.vdd"
= "t.registers.clock_buffer[0].supply.vss" "t.registers.clock_buffer[0].buf1.vss"
= "t.registers.clock_buffer[0].out[0]" "t.registers.clock_buffer[0].out[1]"
= "t.registers.clock_buffer[0].out[0]" "t.registers.clock_buffer[0].buf1.y"
= "t.registers.clock_buffer[0].in" "t.registers.clock_buffer[0].buf1.a"
"t.registers.clock_buffer[1].buf1.a"->"t.registers.clock_buffer[1].buf1._y"-
~("t.registers.clock_buffer[1].buf1.a")->"t.registers.clock_buffer[1].buf1._y"+
"t.registers.clock_buffer[1].buf1._y"->"t.registers.clock_buffer[1].buf1.y"-
~("t.registers.clock_buffer[1].buf1._y")->"t.registers.clock_buffer[1].buf1.y"+
= "t.registers.clock_buffer[1].supply.vdd" "t.registers.clock_buffer[1].buf1.vdd"
= "t.registers.clock_buffer[1].supply.vss" "t.registers.clock_buffer[1].buf1.vss"
= "t.registers.clock_buffer[1].out[0]" "t.registers.clock_buffer[1].out[1]"
= "t.registers.clock_buffer[1].out[0]" "t.registers.clock_buffer[1].buf1.y"
= "t.registers.clock_buffer[1].in" "t.registers.clock_buffer[1].buf1.a"
"t.registers.clock_buffer[2].buf1.a"->"t.registers.clock_buffer[2].buf1._y"-
~("t.registers.clock_buffer[2].buf1.a")->"t.registers.clock_buffer[2].buf1._y"+
"t.registers.clock_buffer[2].buf1._y"->"t.registers.clock_buffer[2].buf1.y"-
~("t.registers.clock_buffer[2].buf1._y")->"t.registers.clock_buffer[2].buf1.y"+
= "t.registers.clock_buffer[2].supply.vdd" "t.registers.clock_buffer[2].buf1.vdd"
= "t.registers.clock_buffer[2].supply.vss" "t.registers.clock_buffer[2].buf1.vss"
= "t.registers.clock_buffer[2].out[0]" "t.registers.clock_buffer[2].out[1]"
= "t.registers.clock_buffer[2].out[0]" "t.registers.clock_buffer[2].buf1.y"
= "t.registers.clock_buffer[2].in" "t.registers.clock_buffer[2].buf1.a"
"t.registers.clock_buffer[3].buf1.a"->"t.registers.clock_buffer[3].buf1._y"-
~("t.registers.clock_buffer[3].buf1.a")->"t.registers.clock_buffer[3].buf1._y"+
"t.registers.clock_buffer[3].buf1._y"->"t.registers.clock_buffer[3].buf1.y"-
~("t.registers.clock_buffer[3].buf1._y")->"t.registers.clock_buffer[3].buf1.y"+
= "t.registers.clock_buffer[3].supply.vdd" "t.registers.clock_buffer[3].buf1.vdd"
= "t.registers.clock_buffer[3].supply.vss" "t.registers.clock_buffer[3].buf1.vss"
= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].out[1]"
= "t.registers.clock_buffer[3].out[0]" "t.registers.clock_buffer[3].buf1.y"
= "t.registers.clock_buffer[3].in" "t.registers.clock_buffer[3].buf1.a"
= "t.registers._in_v_temp" "t.registers.clk_dly.in"
= "t.registers._in_v_temp" "t.registers.val_input_X.in"
= "t.registers._in_v_temp" "t.registers.val_input.out"
= "t.registers._clock" "t.registers.and_encoder[3].b"
= "t.registers._clock" "t.registers.and_encoder[2].b"
= "t.registers._clock" "t.registers.and_encoder[1].b"
= "t.registers._clock" "t.registers.and_encoder[0].b"
= "t.registers._clock" "t.registers.ack_dly.in"
= "t.registers._clock" "t.registers.clk_X.out"
= "t.dly_cfg[0]" "t.registers.dly_cfg[0]"
= "t.dly_cfg[1]" "t.registers.dly_cfg[1]"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"
= "t.in.v" "t.registers.in.v"
= "t.in.a" "t.registers.in.a"
= "t.in.d.d[0].f" "t.registers.in.d.d[0].f"
= "t.in.d.d[0].t" "t.registers.in.d.d[0].t"
= "t.in.d.d[0].d[0]" "t.registers.in.d.d[0].d[0]"
= "t.in.d.d[0].d[1]" "t.registers.in.d.d[0].d[1]"
= "t.in.d.d[1].f" "t.registers.in.d.d[1].f"
= "t.in.d.d[1].t" "t.registers.in.d.d[1].t"
= "t.in.d.d[1].d[0]" "t.registers.in.d.d[1].d[0]"
= "t.in.d.d[1].d[1]" "t.registers.in.d.d[1].d[1]"
= "t.in.d.d[2].f" "t.registers.in.d.d[2].f"
= "t.in.d.d[2].t" "t.registers.in.d.d[2].t"
= "t.in.d.d[2].d[0]" "t.registers.in.d.d[2].d[0]"
= "t.in.d.d[2].d[1]" "t.registers.in.d.d[2].d[1]"
= "t.in.d.d[3].f" "t.registers.in.d.d[3].f"
= "t.in.d.d[3].t" "t.registers.in.d.d[3].t"
= "t.in.d.d[3].d[0]" "t.registers.in.d.d[3].d[0]"
= "t.in.d.d[3].d[1]" "t.registers.in.d.d[3].d[1]"
= "t.in.d.d[4].f" "t.registers.in.d.d[4].f"
= "t.in.d.d[4].t" "t.registers.in.d.d[4].t"
= "t.in.d.d[4].d[0]" "t.registers.in.d.d[4].d[0]"
= "t.in.d.d[4].d[1]" "t.registers.in.d.d[4].d[1]"
= "t.in.d.d[4].d[0]" "t.in.d.d[4].f"
= "t.in.d.d[4].d[1]" "t.in.d.d[4].t"
= "t.in.d.d[3].d[0]" "t.in.d.d[3].f"
= "t.in.d.d[3].d[1]" "t.in.d.d[3].t"
= "t.in.d.d[2].d[0]" "t.in.d.d[2].f"
= "t.in.d.d[2].d[1]" "t.in.d.d[2].t"
= "t.in.d.d[1].d[0]" "t.in.d.d[1].f"
= "t.in.d.d[1].d[1]" "t.in.d.d[1].t"
= "t.in.d.d[0].d[0]" "t.in.d.d[0].f"
= "t.in.d.d[0].d[1]" "t.in.d.d[0].t"