159 lines
6.7 KiB
Verilog
159 lines
6.7 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0encoder1d__bd_35_724_75_74_4(Iin0_d_d0 , Iin0_a , Iin1_d_d0 , Iin1_a , Iin2_d_d0 , Iin2_a , Iin3_d_d0 , Iin3_a , Iin4_d_d0 , Iin4_a , Iin5_d_d0 , Iin5_a , Iin6_d_d0 , Iin6_a , Iin7_d_d0 , Iin7_a , Iin8_d_d0 , Iin8_a , Iin9_d_d0 , Iin9_a , Iin10_d_d0 , Iin10_a , Iin11_d_d0 , Iin11_a , Iin12_d_d0 , Iin12_a , Iin13_d_d0 , Iin13_a , Iin14_d_d0 , Iin14_a , Iin15_d_d0 , Iin15_a , Iin16_d_d0 , Iin16_a , Iin17_d_d0 , Iin17_a , Iin18_d_d0 , Iin18_a , Iin19_d_d0 , Iin19_a , Iin20_d_d0 , Iin20_a , Iin21_d_d0 , Iin21_a , Iin22_d_d0 , Iin22_a , Iin23_d_d0 , Iin23_a , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, Isupply_vss , vdd, vss);
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input vdd;
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input vss;
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input Iin0_d_d0 ;
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input Iin1_d_d0 ;
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input Iin2_d_d0 ;
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input Iin3_d_d0 ;
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input Iin4_d_d0 ;
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input Iin5_d_d0 ;
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input Iin6_d_d0 ;
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input Iin7_d_d0 ;
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input Iin8_d_d0 ;
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input Iin9_d_d0 ;
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input Iin10_d_d0 ;
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input Iin11_d_d0 ;
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input Iin12_d_d0 ;
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input Iin13_d_d0 ;
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input Iin14_d_d0 ;
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input Iin15_d_d0 ;
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input Iin16_d_d0 ;
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input Iin17_d_d0 ;
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input Iin18_d_d0 ;
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input Iin19_d_d0 ;
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input Iin20_d_d0 ;
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input Iin21_d_d0 ;
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input Iin22_d_d0 ;
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input Iin23_d_d0 ;
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input Iout_a ;
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input Idly_cfg0 ;
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input Idly_cfg1 ;
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input Idly_cfg2 ;
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input Idly_cfg3 ;
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input reset_B;
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input Isupply_vss ;
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// -- signals ---
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wire Iin9_d_d0 ;
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wire Iin20_d_d0 ;
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output Iin11_a ;
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wire Iin4_d_d0 ;
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wire I_fifo_out_d_d0_d1 ;
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wire Iin19_d_d0 ;
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output Iin10_a ;
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wire Iin10_d_d0 ;
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output Iout_d3 ;
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wire I_fifo_out_d_d1_d1 ;
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wire Iin21_d_d0 ;
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wire Iin6_d_d0 ;
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output Iin15_a ;
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wire I_enc_out_d_d2_d0 ;
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wire I_enc_out_d_d0_d0 ;
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output Iin8_a ;
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output Iin6_a ;
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wire Iin3_d_d0 ;
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output Iin2_a ;
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wire I_enc_out_d_d3_d1 ;
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wire I_fifo_out_d_d1_d0 ;
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wire Iin12_d_d0 ;
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wire I_enc_out_d_d4_d1 ;
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wire I_fifo_out_d_d0_d0 ;
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wire I_enc_out_v ;
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wire I_fifo_out_d_d3_d0 ;
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wire I_enc_out_d_d3_d0 ;
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output Iout_d4 ;
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output Iin22_a ;
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wire _reset_BX ;
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wire Iout_a ;
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wire I_fifo_out_v ;
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wire Iin5_d_d0 ;
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output Iin1_a ;
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wire Idly_cfg1 ;
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wire I_fifo_out_d_d2_d0 ;
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wire Iin14_d_d0 ;
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output Iin7_a ;
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output Iin5_a ;
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wire I_enc_out_d_d4_d0 ;
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output Iin21_a ;
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output Iin9_a ;
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wire I_fifo_out_d_d4_d0 ;
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output Iin13_a ;
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output Iin4_a ;
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wire I_enc_out_d_d2_d1 ;
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wire I_enc_out_d_d0_d1 ;
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output Iout_d1 ;
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wire Idly_cfg0 ;
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wire Iin18_d_d0 ;
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wire Iin16_d_d0 ;
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output Iin12_a ;
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wire Iin2_d_d0 ;
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wire I_enc_out_d_d1_d0 ;
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output Iin0_a ;
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wire I_fifo_out_a ;
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wire Iin15_d_d0 ;
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output Iin14_a ;
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wire Iin8_d_d0 ;
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wire Iin7_d_d0 ;
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wire Iin23_d_d0 ;
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output Iin20_a ;
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wire Isupply_vss ;
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wire I_fifo_out_d_d2_d1 ;
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wire reset_B;
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output Iin18_a ;
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wire I_enc_out_d_d1_d1 ;
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wire Iin22_d_d0 ;
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output Iin16_a ;
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wire Iin1_d_d0 ;
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wire Idly_cfg3 ;
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wire I_enc_out_a ;
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wire Idly_cfg2 ;
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output Iin3_a ;
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output Iin23_a ;
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output Iout_d2 ;
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output Iout_d0 ;
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output Iin17_a ;
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wire Iin0_d_d0 ;
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output Iout_r ;
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output Iin19_a ;
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wire I_fifo_out_d_d3_d1 ;
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wire I_fifo_out_d_d4_d1 ;
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wire Iin17_d_d0 ;
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wire Iin13_d_d0 ;
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wire Iin11_d_d0 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4 I_qdi2bd (.Iin_d_d0_d0 (I_fifo_out_d_d0_d0 ), .Iin_d_d0_d1 (I_fifo_out_d_d0_d1 ), .Iin_d_d1_d0 (I_fifo_out_d_d1_d0 ), .Iin_d_d1_d1 (I_fifo_out_d_d1_d1 ), .Iin_d_d2_d0 (I_fifo_out_d_d2_d0 ), .Iin_d_d2_d1 (I_fifo_out_d_d2_d1 ), .Iin_d_d3_d0 (I_fifo_out_d_d3_d0 ), .Iin_d_d3_d1 (I_fifo_out_d_d3_d1 ), .Iin_d_d4_d0 (I_fifo_out_d_d4_d0 ), .Iin_d_d4_d1 (I_fifo_out_d_d4_d1 ), .Iin_a (I_fifo_out_a ), .Iin_v (I_fifo_out_v ), .Iout_d0 (Iout_d0 ), .Iout_d1 (Iout_d1 ), .Iout_d2 (Iout_d2 ), .Iout_d3 (Iout_d3 ), .Iout_d4 (Iout_d4 ), .Iout_r (Iout_r ), .Iout_a (Iout_a ), .Idly_cfg0 (Idly_cfg0 ), .Idly_cfg1 (Idly_cfg1 ), .Idly_cfg2 (Idly_cfg2 ), .Idly_cfg3 (Idly_cfg3 ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0fifo_35_75_4 I_fifo (.Iin_d_d0_d0 (I_enc_out_d_d0_d0 ), .Iin_d_d0_d1 (I_enc_out_d_d0_d1 ), .Iin_d_d1_d0 (I_enc_out_d_d1_d0 ), .Iin_d_d1_d1 (I_enc_out_d_d1_d1 ), .Iin_d_d2_d0 (I_enc_out_d_d2_d0 ), .Iin_d_d2_d1 (I_enc_out_d_d2_d1 ), .Iin_d_d3_d0 (I_enc_out_d_d3_d0 ), .Iin_d_d3_d1 (I_enc_out_d_d3_d1 ), .Iin_d_d4_d0 (I_enc_out_d_d4_d0 ), .Iin_d_d4_d1 (I_enc_out_d_d4_d1 ), .Iin_a (I_enc_out_a ), .Iin_v (I_enc_out_v ), .Iout_d_d0_d0 (I_fifo_out_d_d0_d0 ), .Iout_d_d0_d1 (I_fifo_out_d_d0_d1 ), .Iout_d_d1_d0 (I_fifo_out_d_d1_d0 ), .Iout_d_d1_d1 (I_fifo_out_d_d1_d1 ), .Iout_d_d2_d0 (I_fifo_out_d_d2_d0 ), .Iout_d_d2_d1 (I_fifo_out_d_d2_d1 ), .Iout_d_d3_d0 (I_fifo_out_d_d3_d0 ), .Iout_d_d3_d1 (I_fifo_out_d_d3_d1 ), .Iout_d_d4_d0 (I_fifo_out_d_d4_d0 ), .Iout_d_d4_d1 (I_fifo_out_d_d4_d1 ), .Iout_a (I_fifo_out_a ), .Iout_v (I_fifo_out_v ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0encoder1d__simple_35_724_4 I_enc (.Iin0_d_d0 (Iin0_d_d0 ), .Iin0_a (Iin0_a ), .Iin1_d_d0 (Iin1_d_d0 ), .Iin1_a (Iin1_a ), .Iin2_d_d0 (Iin2_d_d0 ), .Iin2_a (Iin2_a ), .Iin3_d_d0 (Iin3_d_d0 ), .Iin3_a (Iin3_a ), .Iin4_d_d0 (Iin4_d_d0 ), .Iin4_a (Iin4_a ), .Iin5_d_d0 (Iin5_d_d0 ), .Iin5_a (Iin5_a ), .Iin6_d_d0 (Iin6_d_d0 ), .Iin6_a (Iin6_a ), .Iin7_d_d0 (Iin7_d_d0 ), .Iin7_a (Iin7_a ), .Iin8_d_d0 (Iin8_d_d0 ), .Iin8_a (Iin8_a ), .Iin9_d_d0 (Iin9_d_d0 ), .Iin9_a (Iin9_a ), .Iin10_d_d0 (Iin10_d_d0 ), .Iin10_a (Iin10_a ), .Iin11_d_d0 (Iin11_d_d0 ), .Iin11_a (Iin11_a ), .Iin12_d_d0 (Iin12_d_d0 ), .Iin12_a (Iin12_a ), .Iin13_d_d0 (Iin13_d_d0 ), .Iin13_a (Iin13_a ), .Iin14_d_d0 (Iin14_d_d0 ), .Iin14_a (Iin14_a ), .Iin15_d_d0 (Iin15_d_d0 ), .Iin15_a (Iin15_a ), .Iin16_d_d0 (Iin16_d_d0 ), .Iin16_a (Iin16_a ), .Iin17_d_d0 (Iin17_d_d0 ), .Iin17_a (Iin17_a ), .Iin18_d_d0 (Iin18_d_d0 ), .Iin18_a (Iin18_a ), .Iin19_d_d0 (Iin19_d_d0 ), .Iin19_a (Iin19_a ), .Iin20_d_d0 (Iin20_d_d0 ), .Iin20_a (Iin20_a ), .Iin21_d_d0 (Iin21_d_d0 ), .Iin21_a (Iin21_a ), .Iin22_d_d0 (Iin22_d_d0 ), .Iin22_a (Iin22_a ), .Iin23_d_d0 (Iin23_d_d0 ), .Iin23_a (Iin23_a ), .Iout_d_d0_d0 (I_enc_out_d_d0_d0 ), .Iout_d_d0_d1 (I_enc_out_d_d0_d1 ), .Iout_d_d1_d0 (I_enc_out_d_d1_d0 ), .Iout_d_d1_d1 (I_enc_out_d_d1_d1 ), .Iout_d_d2_d0 (I_enc_out_d_d2_d0 ), .Iout_d_d2_d1 (I_enc_out_d_d2_d1 ), .Iout_d_d3_d0 (I_enc_out_d_d3_d0 ), .Iout_d_d3_d1 (I_enc_out_d_d3_d1 ), .Iout_d_d4_d0 (I_enc_out_d_d4_d0 ), .Iout_d_d4_d1 (I_enc_out_d_d4_d1 ), .Iout_a (I_enc_out_a ), .Iout_v (I_enc_out_v ), .Isupply_vss (Isupply_vss ), .reset_B(_reset_BX), .vdd(vdd), .vss(vss));
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BUF_X4 Irsb (.y(_reset_BX), .a(reset_B), .vdd(vdd), .vss(vss));
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endmodule |