150 lines
2.2 KiB
Plaintext
150 lines
2.2 KiB
Plaintext
watchall
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set c.bd_dly_cfg[0] 1
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set c.bd_dly_cfg[1] 1
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set c.bd_dly_cfg[2] 1
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set c.bd_dly_cfg[3] 1
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set c.bd_dly_cfg2[0] 1
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set c.bd_dly_cfg2[1] 1
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set-bd-channel-neutral "c.in" 14
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set c.out.a 0
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set c.loopback_en 1
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set Reset 1
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cycle
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mode run
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status X
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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# Reading address 0
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set c.in.d[0] 0
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set c.in.d[1] 0
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set c.in.d[2] 0
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set c.in.d[3] 0
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set c.in.d[4] 0
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set c.in.d[5] 0
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set c.in.d[6] 0
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set c.in.d[7] 0
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set c.in.d[8] 0
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set c.in.d[9] 0
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set c.in.d[10] 0
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set c.in.d[11] 0
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set c.in.d[12] 0
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set c.in.d[13] 1
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Should first get loopback
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assert-bd-channel-valid "c.out" 14 8192
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Expect register read packet to arrive
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assert-bd-channel-valid "c.out" 14 4080
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Disable loopback cus it's annoying
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set c.loopback_en 0
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cycle
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# Writing 68 to address 1
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set c.in.d[0] 1
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set c.in.d[1] 0
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set c.in.d[2] 0
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set c.in.d[3] 0
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set c.in.d[4] 0
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set c.in.d[5] 0
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set c.in.d[6] 1
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set c.in.d[7] 0
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set c.in.d[8] 0
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set c.in.d[9] 0
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set c.in.d[10] 1
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set c.in.d[11] 0
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set c.in.d[12] 1
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set c.in.d[13] 1
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Reading address 1
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set c.in.d[0] 1
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set c.in.d[1] 0
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set c.in.d[2] 0
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set c.in.d[3] 0
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set c.in.d[4] 0
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set c.in.d[5] 0
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set c.in.d[6] 0
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set c.in.d[7] 0
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set c.in.d[8] 0
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set c.in.d[9] 0
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set c.in.d[10] 0
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set c.in.d[11] 0
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set c.in.d[12] 0
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set c.in.d[13] 1
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 14
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cycle
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assert c.in.a 0
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# Receiving output 68 from register 1
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assert-bd-channel-valid "c.out" 14 1089
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 14
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set c.out.a 0
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cycle
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# Sending spike to synapse [0,1]
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set c.in.d[0] 0
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set c.in.d[1] 1
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set c.in.d[2] 0
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set c.in.d[3] 0
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set c.in.d[4] 0
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set c.in.d[5] 0
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set c.in.d[6] 0
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set c.in.d[7] 0
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set c.in.d[8] 0
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set c.in.d[9] 0
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set c.in.d[10] 0
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set c.in.d[11] 0
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set c.in.d[12] 0
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set c.in.d[13] 0
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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