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actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0.../netlist/verilog.v

350 lines
16 KiB
Verilog
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module tmpl_0_0dataflow__neuro_0_0dropper__static_332_7f_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iin_d_d29_d0 , Iin_d_d29_d1 , Iin_d_d30_d0 , Iin_d_d30_d1 , Iin_d_d31_d0 , Iin_d_d31_d1 , Iin_a , Iin_v , Iout_d_d0_d0 , Iout_d_d0_d1 , Iout_d_d1_d0 , Iout_d_d1_d1 , Iout_d_d2_d0 , Iout_d_d2_d1 , Iout_d_d3_d0 , Iout_d_d3_d1 , Iout_d_d4_d0 , Iout_d_d4_d1 , Iout_d_d5_d0 , Iout_d_d5_d1 , Iout_d_d6_d0 , Iout_d_d6_d1 , Iout_d_d7_d0 , Iout_d_d7_d1 , Iout_d_d8_d0 , Iout_d_d8_d1 , Iout_d_d9_d0 , Iout_d_d9_d1 , Iout_d_d10_d0 , Iout_d_d10_d1 , Iout_d_d11_d0 , Iout_d_d11_d1 , Iout_d_d12_d0 , Iout_d_d12_d1 , Iout_d_d13_d0 , Iout_d_d13_d1 , Iout_d_d14_d0 , Iout_d_d14_d1 , Iout_d_d15_d0 , Iout_d_d15_d1 , Iout_d_d16_d0 , Iout_d_d16_d1 , Iout_d_d17_d0 , Iout_d_d17_d1 , Iout_d_d18_d0 , Iout_d_d18_d1 , Iout_d_d19_d0 , Iout_d_d19_d1 , Iout_d_d20_d0 , Iout_d_d20_d1 , Iout_d_d21_d0 , Iout_d_d21_d1 , Iout_d_d22_d0 , Iout_d_d22_d1 , Iout_d_d23_d0 , Iout_d_d23_d1 , Iout_d_d24_d0 , Iout_d_d24_d1 , Iout_d_d25_d0 , Iout_d_d25_d1 , Iout_d_d26_d0 , Iout_d_d26_d1 , Iout_d_d27_d0 , Iout_d_d27_d1 , Iout_d_d28_d0 , Iout_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Iout_d_d30_d1 , Iout_d_d31_d0 , Iout_d_d31_d1 , Iout_a , cond, vdd, vss);
input vdd;
input vss;
input Iin_d_d0_d0 ;
input Iin_d_d0_d1 ;
input Iin_d_d1_d0 ;
input Iin_d_d1_d1 ;
input Iin_d_d2_d0 ;
input Iin_d_d2_d1 ;
input Iin_d_d3_d0 ;
input Iin_d_d3_d1 ;
input Iin_d_d4_d0 ;
input Iin_d_d4_d1 ;
input Iin_d_d5_d0 ;
input Iin_d_d5_d1 ;
input Iin_d_d6_d0 ;
input Iin_d_d6_d1 ;
input Iin_d_d7_d0 ;
input Iin_d_d7_d1 ;
input Iin_d_d8_d0 ;
input Iin_d_d8_d1 ;
input Iin_d_d9_d0 ;
input Iin_d_d9_d1 ;
input Iin_d_d10_d0 ;
input Iin_d_d10_d1 ;
input Iin_d_d11_d0 ;
input Iin_d_d11_d1 ;
input Iin_d_d12_d0 ;
input Iin_d_d12_d1 ;
input Iin_d_d13_d0 ;
input Iin_d_d13_d1 ;
input Iin_d_d14_d0 ;
input Iin_d_d14_d1 ;
input Iin_d_d15_d0 ;
input Iin_d_d15_d1 ;
input Iin_d_d16_d0 ;
input Iin_d_d16_d1 ;
input Iin_d_d17_d0 ;
input Iin_d_d17_d1 ;
input Iin_d_d18_d0 ;
input Iin_d_d18_d1 ;
input Iin_d_d19_d0 ;
input Iin_d_d19_d1 ;
input Iin_d_d20_d0 ;
input Iin_d_d20_d1 ;
input Iin_d_d21_d0 ;
input Iin_d_d21_d1 ;
input Iin_d_d22_d0 ;
input Iin_d_d22_d1 ;
input Iin_d_d23_d0 ;
input Iin_d_d23_d1 ;
input Iin_d_d24_d0 ;
input Iin_d_d24_d1 ;
input Iin_d_d25_d0 ;
input Iin_d_d25_d1 ;
input Iin_d_d26_d0 ;
input Iin_d_d26_d1 ;
input Iin_d_d27_d0 ;
input Iin_d_d27_d1 ;
input Iin_d_d28_d0 ;
input Iin_d_d28_d1 ;
input Iin_d_d29_d0 ;
input Iin_d_d29_d1 ;
input Iin_d_d30_d0 ;
input Iin_d_d30_d1 ;
input Iin_d_d31_d0 ;
input Iin_d_d31_d1 ;
input Iout_a ;
input cond;
// -- signals ---
output Iout_d_d1_d1 ;
wire Iin_d_d9_d1 ;
output Iin_a ;
wire Iin_d_d7_d0 ;
wire Iin_d_d13_d0 ;
wire Iin_d_d4_d1 ;
output Iout_d_d1_d0 ;
wire Iin_d_d14_d1 ;
wire Iin_d_d1_d1 ;
wire Iin_d_d2_d1 ;
wire Iin_d_d19_d1 ;
output Iout_d_d29_d1 ;
wire Iout_a ;
output Iout_d_d13_d1 ;
wire Iin_d_d27_d1 ;
wire Iin_d_d27_d0 ;
wire Iin_d_d8_d1 ;
wire Iin_d_d21_d1 ;
output Iout_d_d24_d0 ;
output Iout_d_d12_d1 ;
output Iout_d_d15_d1 ;
wire _in_vX ;
wire _drop ;
wire Iin_d_d3_d0 ;
output Iout_d_d26_d0 ;
wire Iin_d_d15_d1 ;
output Iout_d_d19_d0 ;
wire cond;
wire Iin_d_d14_d0 ;
output Iout_d_d3_d0 ;
output Iout_d_d19_d1 ;
output Iout_d_d4_d1 ;
output Iout_d_d18_d1 ;
output Iout_d_d2_d0 ;
output Iout_d_d14_d1 ;
wire Iin_d_d17_d1 ;
wire Iin_d_d28_d1 ;
wire Ior2_b ;
output Iout_d_d14_d0 ;
output Iout_d_d3_d1 ;
wire Iin_d_d1_d0 ;
wire Iin_d_d31_d0 ;
wire Iin_d_d22_d1 ;
wire Iin_d_d12_d1 ;
output Iout_d_d23_d1 ;
output Iout_d_d28_d1 ;
wire Iin_d_d0_d0 ;
wire Iin_d_d18_d0 ;
wire Iin_d_d29_d0 ;
output Iout_d_d0_d1 ;
wire Iin_d_d10_d0 ;
wire Iin_d_d0_d1 ;
wire Iand_f31_b ;
output Iout_d_d0_d0 ;
wire Iin_d_d11_d0 ;
output Iout_d_d22_d0 ;
wire Ivt_out ;
output Iout_d_d4_d0 ;
output Iout_d_d18_d0 ;
output Iout_d_d16_d1 ;
output Iout_d_d17_d1 ;
output Iout_d_d13_d0 ;
wire Iin_d_d6_d1 ;
output Iout_d_d7_d1 ;
wire Iin_d_d2_d0 ;
output Iout_d_d5_d0 ;
wire Iin_d_d17_d0 ;
output Iout_d_d27_d1 ;
output Iout_d_d20_d1 ;
wire Iin_d_d24_d1 ;
output Iout_d_d31_d1 ;
output Iout_d_d9_d0 ;
output Iout_d_d28_d0 ;
wire Iin_d_d31_d1 ;
wire Ior2_y ;
output Iout_d_d12_d0 ;
wire Iin_d_d16_d0 ;
wire Iin_d_d20_d0 ;
wire Iin_d_d21_d0 ;
output Iout_d_d31_d0 ;
output Iout_d_d11_d0 ;
output Iout_d_d27_d0 ;
wire Iin_d_d30_d1 ;
wire Iin_d_d12_d0 ;
wire Iin_d_d25_d1 ;
wire Iin_d_d29_d1 ;
output Iout_d_d15_d0 ;
output Iout_d_d16_d0 ;
wire Iin_d_d23_d1 ;
wire Iin_d_d20_d1 ;
output Iout_d_d10_d0 ;
output Iout_d_d17_d0 ;
output Iout_d_d6_d1 ;
output Iout_d_d23_d0 ;
wire Iin_d_d10_d1 ;
wire Iin_d_d26_d1 ;
wire Iin_d_d5_d0 ;
wire Iin_d_d22_d0 ;
wire Iin_d_d5_d1 ;
output Iout_d_d26_d1 ;
output Iout_d_d6_d0 ;
output Iout_d_d7_d0 ;
output Iout_d_d8_d0 ;
output Iout_d_d8_d1 ;
output Iout_d_d21_d1 ;
wire Iin_d_d28_d0 ;
output Iout_d_d2_d1 ;
output Iout_d_d22_d1 ;
output Iout_d_d21_d0 ;
wire Iin_d_d30_d0 ;
wire Iin_d_d16_d1 ;
output Iout_d_d10_d1 ;
wire Iin_d_d19_d0 ;
output Iout_d_d11_d1 ;
wire Iin_d_d18_d1 ;
output Iout_d_d20_d0 ;
output Iout_d_d25_d0 ;
wire Iin_d_d25_d0 ;
output Iout_d_d29_d0 ;
output Iout_d_d30_d1 ;
wire Iin_d_d23_d0 ;
wire Iin_d_d8_d0 ;
wire Iin_d_d15_d0 ;
wire Iin_d_d4_d0 ;
wire Iin_d_d24_d0 ;
output Iin_v ;
wire Iin_d_d6_d0 ;
wire Iin_d_d3_d1 ;
wire Iin_d_d13_d1 ;
output Iout_d_d24_d1 ;
output Iout_d_d25_d1 ;
output Iout_d_d9_d1 ;
wire Iin_d_d26_d0 ;
output Iout_d_d30_d0 ;
wire Iin_d_d7_d1 ;
wire Iin_d_d11_d1 ;
wire Iin_d_d9_d0 ;
output Iout_d_d5_d1 ;
// --- instances
BUF_X4 Iin_v_buf (.y(_in_vX), .a(Ivt_out ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_364_4 Isb_dropB (.in(cond), .Iout0 (Iand_f31_b ), .vdd(vdd), .vss(vss));
OR2_X1 Ior2 (.y(Ior2_y ), .a(Iout_a ), .b(Ior2_b ), .vdd(vdd), .vss(vss));
AND2_X1 Iand2 (.y(Ior2_b ), .a(_drop), .b(_in_vX), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_365_4 Isb_in_v (.in(_in_vX), .Iout0 (Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f0 (.y(Iout_d_d0_d0 ), .a(Iin_d_d0_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f1 (.y(Iout_d_d1_d0 ), .a(Iin_d_d1_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f2 (.y(Iout_d_d2_d0 ), .a(Iin_d_d2_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f3 (.y(Iout_d_d3_d0 ), .a(Iin_d_d3_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f4 (.y(Iout_d_d4_d0 ), .a(Iin_d_d4_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f5 (.y(Iout_d_d5_d0 ), .a(Iin_d_d5_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f6 (.y(Iout_d_d6_d0 ), .a(Iin_d_d6_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f7 (.y(Iout_d_d7_d0 ), .a(Iin_d_d7_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f8 (.y(Iout_d_d8_d0 ), .a(Iin_d_d8_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f9 (.y(Iout_d_d9_d0 ), .a(Iin_d_d9_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f10 (.y(Iout_d_d10_d0 ), .a(Iin_d_d10_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f11 (.y(Iout_d_d11_d0 ), .a(Iin_d_d11_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f12 (.y(Iout_d_d12_d0 ), .a(Iin_d_d12_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f13 (.y(Iout_d_d13_d0 ), .a(Iin_d_d13_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f14 (.y(Iout_d_d14_d0 ), .a(Iin_d_d14_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f15 (.y(Iout_d_d15_d0 ), .a(Iin_d_d15_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f16 (.y(Iout_d_d16_d0 ), .a(Iin_d_d16_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f17 (.y(Iout_d_d17_d0 ), .a(Iin_d_d17_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f18 (.y(Iout_d_d18_d0 ), .a(Iin_d_d18_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f19 (.y(Iout_d_d19_d0 ), .a(Iin_d_d19_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f20 (.y(Iout_d_d20_d0 ), .a(Iin_d_d20_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f21 (.y(Iout_d_d21_d0 ), .a(Iin_d_d21_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f22 (.y(Iout_d_d22_d0 ), .a(Iin_d_d22_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f23 (.y(Iout_d_d23_d0 ), .a(Iin_d_d23_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f24 (.y(Iout_d_d24_d0 ), .a(Iin_d_d24_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f25 (.y(Iout_d_d25_d0 ), .a(Iin_d_d25_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f26 (.y(Iout_d_d26_d0 ), .a(Iin_d_d26_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f27 (.y(Iout_d_d27_d0 ), .a(Iin_d_d27_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f28 (.y(Iout_d_d28_d0 ), .a(Iin_d_d28_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f29 (.y(Iout_d_d29_d0 ), .a(Iin_d_d29_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f30 (.y(Iout_d_d30_d0 ), .a(Iin_d_d30_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_f31 (.y(Iout_d_d31_d0 ), .a(Iin_d_d31_d0 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t0 (.y(Iout_d_d0_d1 ), .a(Iin_d_d0_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t1 (.y(Iout_d_d1_d1 ), .a(Iin_d_d1_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t2 (.y(Iout_d_d2_d1 ), .a(Iin_d_d2_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t3 (.y(Iout_d_d3_d1 ), .a(Iin_d_d3_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t4 (.y(Iout_d_d4_d1 ), .a(Iin_d_d4_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t5 (.y(Iout_d_d5_d1 ), .a(Iin_d_d5_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t6 (.y(Iout_d_d6_d1 ), .a(Iin_d_d6_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t7 (.y(Iout_d_d7_d1 ), .a(Iin_d_d7_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t8 (.y(Iout_d_d8_d1 ), .a(Iin_d_d8_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t9 (.y(Iout_d_d9_d1 ), .a(Iin_d_d9_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t10 (.y(Iout_d_d10_d1 ), .a(Iin_d_d10_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t11 (.y(Iout_d_d11_d1 ), .a(Iin_d_d11_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t12 (.y(Iout_d_d12_d1 ), .a(Iin_d_d12_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t13 (.y(Iout_d_d13_d1 ), .a(Iin_d_d13_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t14 (.y(Iout_d_d14_d1 ), .a(Iin_d_d14_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t15 (.y(Iout_d_d15_d1 ), .a(Iin_d_d15_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t16 (.y(Iout_d_d16_d1 ), .a(Iin_d_d16_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t17 (.y(Iout_d_d17_d1 ), .a(Iin_d_d17_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t18 (.y(Iout_d_d18_d1 ), .a(Iin_d_d18_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t19 (.y(Iout_d_d19_d1 ), .a(Iin_d_d19_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t20 (.y(Iout_d_d20_d1 ), .a(Iin_d_d20_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t21 (.y(Iout_d_d21_d1 ), .a(Iin_d_d21_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t22 (.y(Iout_d_d22_d1 ), .a(Iin_d_d22_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t23 (.y(Iout_d_d23_d1 ), .a(Iin_d_d23_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t24 (.y(Iout_d_d24_d1 ), .a(Iin_d_d24_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t25 (.y(Iout_d_d25_d1 ), .a(Iin_d_d25_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t26 (.y(Iout_d_d26_d1 ), .a(Iin_d_d26_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t27 (.y(Iout_d_d27_d1 ), .a(Iin_d_d27_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t28 (.y(Iout_d_d28_d1 ), .a(Iin_d_d28_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t29 (.y(Iout_d_d29_d1 ), .a(Iin_d_d29_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t30 (.y(Iout_d_d30_d1 ), .a(Iin_d_d30_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
AND3_X1 Iand_t31 (.y(Iout_d_d31_d1 ), .a(Iin_d_d31_d1 ), .b(Iand_f31_b ), .c(Iin_v ), .vdd(vdd), .vss(vss));
INV_X1 Iinv (.y(_drop), .a(cond), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_332_4 Ivt (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .Iin_d29_d0 (Iin_d_d29_d0 ), .Iin_d29_d1 (Iin_d_d29_d1 ), .Iin_d30_d0 (Iin_d_d30_d0 ), .Iin_d30_d1 (Iin_d_d30_d1 ), .Iin_d31_d0 (Iin_d_d31_d0 ), .Iin_d31_d1 (Iin_d_d31_d1 ), .out(Ivt_out ), .vdd(vdd), .vss(vss));
A_2C_B_X1 Iack_Cel (.y(Iin_a ), .c1(Ior2_y ), .c2(_in_vX), .vdd(vdd), .vss(vss));
endmodule
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