48 lines
1.4 KiB
Verilog
48 lines
1.4 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_38_746_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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input Iin5 ;
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input Iin6 ;
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input Iin7 ;
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// -- signals ---
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output Iout7 ;
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output Iout3 ;
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output Iout0 ;
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output Iout1 ;
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wire Iin1 ;
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wire Iin2 ;
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output Iout4 ;
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wire Iin4 ;
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output Iout6 ;
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wire Iin7 ;
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wire Iin0 ;
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wire Iin3 ;
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output Iout5 ;
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output Iout2 ;
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wire Iin5 ;
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wire Iin6 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb0 (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb1 (.in(Iin1 ), .Iout0 (Iout1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb2 (.in(Iin2 ), .Iout0 (Iout2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb3 (.in(Iin3 ), .Iout0 (Iout3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb4 (.in(Iin4 ), .Iout0 (Iout4 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb5 (.in(Iin5 ), .Iout0 (Iout5 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb6 (.in(Iin6 ), .Iout0 (Iout6 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb7 (.in(Iin7 ), .Iout0 (Iout7 ), .vdd(vdd), .vss(vss));
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endmodule |