403 lines
8.0 KiB
Plaintext
403 lines
8.0 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2020-2021 Rajit Manohar
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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namespace tmpl {
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namespace dataflow_neuro {
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export defproc TIELO_X1(bool! y; bool vdd, vss)
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{
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y = vss;
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}
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export defproc TIEHI_X1(bool! y; bool vdd, vss)
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{
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y = vdd;
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}
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/*-- inverters --*/
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defproc inv (bool! y; bool? a, vdd, vss)
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{
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prs {
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a => y-
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}
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}
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template<pint nf>
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defproc szinv <: inv()
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{
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[nf = 0 -> sizing { y {-1} }
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[] else -> sizing { y {-2*nf,svt,nf} }
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]
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}
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export defcell INV_X1<: szinv<0>() { }
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export defcell INV_X2<: szinv<1>() { }
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export defcell INV_X4<: szinv<2>() { }
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export defcell INV_X8<: szinv<4>() { }
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/*-- signal buffers --*/
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defproc buf (bool! y; bool? a, vdd, vss)
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{
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bool _y;
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prs {
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a => _y-
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_y => y-
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}
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}
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export defcell BUF_X1<: buf()
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{
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sizing { _y {-1}; y {-1} }
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}
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export defcell BUF_X2<: buf()
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{
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sizing { _y {-1}; y {-2} }
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}
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export defcell BUF_X3<: buf()
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{
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sizing { _y {-1.5}; y {-3} }
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}
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export defcell BUF_X4<: buf()
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{
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sizing { _y {-1.5}; y {-4,2} }
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}
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export defcell BUF_X6<: buf()
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{
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sizing { _y {-3}; y {-6,2} }
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}
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export defcell BUF_X8<: buf()
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{
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sizing { _y {-4,2}; y {-8,4} }
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}
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export defcell BUF_X12<: buf()
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{
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sizing { _y {-6,2}; y {-12,4} }
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}
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/*-- delay cells --*/
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// TODO properly
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export defcell DLY4_X1(bool! y; bool? a, vdd, vss)
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{
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bool _y, __y, ___y;
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prs {
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a => _y-
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_y => __y-
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__y => ___y-
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___y => y-
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}
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}
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/*-- simple gates --*/
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export defcell NOR2_X1(bool! y; bool? a, b, vdd, vss)
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{
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prs {
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a | b => y-
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}
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sizing { y {-1} }
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}
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export defcell NOR3_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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prs {
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a | b | c => y-
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}
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sizing { y {-1} }
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}
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export defcell NOR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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prs {
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a | b | c | d => y-
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}
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sizing { y {-1} }
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}
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export defcell OR2_X1(bool! y; bool? a, b, vdd, vss)
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{
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bool _y;
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prs {
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a | b => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell OR2_X2(bool! y; bool? a, b, vdd, vss)
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{
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bool _y;
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prs {
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a | b => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-2} }
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}
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export defcell OR3_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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bool _y;
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prs {
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a | b | c => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell OR4_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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bool _y;
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prs {
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a | b | c | d => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell NAND2_X1(bool! y; bool? a, b, vdd, vss)
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{
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prs {
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a & b => y-
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}
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sizing { y{-1} }
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}
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export defcell NAND3_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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prs {
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a & b & c => y-
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}
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sizing { y{-1} }
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}
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export defcell NAND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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prs {
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a & b & c & d => y-
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}
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sizing { y{-1} }
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}
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export defcell AND2_X1(bool! y; bool? a, b, vdd, vss)
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{
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bool _y;
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prs {
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a & b => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell AND2_X2(bool! y; bool? a, b, vdd, vss)
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{
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bool _y;
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prs {
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a & b => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-2} }
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}
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export defcell AND3_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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bool _y;
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prs {
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a & b & c => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell AND4_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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bool _y;
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prs {
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a & b & c & d => _y-
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_y => y-
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}
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sizing { _y{-1}; y{-1} }
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}
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export defcell XOR2_X1(bool! y; bool? a, b, vdd, vss)
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{
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bool _a, _b;
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prs {
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a => _a-
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b => _b-
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[keeper=0] ~b & ~_a | ~_b & ~a -> y+
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_b & _a | b & a -> y-
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}
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sizing { _a{-1}; _b{-1}; y{-1} }
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}
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export defcell XNOR2_X1(bool! y; bool? a, b, vdd, vss)
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{
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bool _a, _b;
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prs {
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a => _a-
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b => _b-
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[keeper=0] ~b & ~a | ~_b & ~_a -> y+
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b & _a | _b & a -> y-
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}
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sizing { _a{-1}; _b{-1}; y{-1} }
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}
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export defcell MUX2_X1(bool! y; bool? a, b, s, vdd, vss)
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{
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// y = !( S ? b : a )
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// Adjusted to fit the XFAB Muxes
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bool _s;
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bool _y;
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prs {
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s => _s-
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[keeper=0] ~a & ~s | ~b & ~_s -> _y+
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a & _s | b & s -> _y-
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_y => y-
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}
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sizing { _s{-1}; y{-1}; _y{-1}}
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}
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export defcell MUX4_X1(bool! y; bool? a, b, c, d, s0, s1, vdd, vss)
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{
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// y = !( S ? a : b )
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bool _s0;
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bool _s1;
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bool _yab;
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bool _ycd;
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prs {
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s0 => _s0-
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s1 => _s1-
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[keeper=0] a & _s0 | b & s0 -> _yab-
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~a & ~s0 | ~b & ~_s0 -> _yab+
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[keeper=0] c & _s0 | d & s0 -> _ycd-
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~c & ~s0 | ~d & ~_s0 -> _ycd+
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[keeper=0]_yab & _s1 | _ycd & s1 -> y-
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~_yab & ~s1 | ~_ycd & ~_s1 -> y+
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}
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sizing {_s0{-1}; _s1{-1}; y{-1}; _yab{-1}; _ycd{-1}}
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}
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export defcell OAI21_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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prs {
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(a | b) & c => y-
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}
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sizing { y{-1} }
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}
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export defcell AOI21_X1(bool! y; bool? a, b, c, vdd, vss)
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{
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prs {
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a & b | c => y-
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}
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sizing { y{-1} }
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}
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export defcell OAI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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// y = !((a|b) & (c|d))
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prs {
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(a | b) & (c | d) => y-
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}
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sizing { y{-1} }
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}
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export defcell AOI22_X1(bool! y; bool? a, b, c, d, vdd, vss)
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{
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prs {
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a & b | c & d => y-
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}
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sizing { y{-1} }
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}
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/*--- buffered transmission gates ---*/
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export defcell TBUF1_X1 (bool! y; bool? a, en, vdd, vss)
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{
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bool _en;
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prs {
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en => _en-
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~a & ~_en -> y+
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a & en -> y-
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}
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sizing { _en{-1}; y{-1} }
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}
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export defcell TBUF_X2 (bool! y; bool? a, en, vdd, vss)
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{
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bool _en;
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prs {
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en => _en-
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~a & ~_en -> y+
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a & en -> y-
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}
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sizing { _en{-2}; y{-2,2} }
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}
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export defproc DFFQ_R_X1 (bool? clk, reset_B, d; bool! q; bool? vdd,vss)
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{
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bool _clk, __clk, _mqi,_mqib,_sqi,_sqib;
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prs {
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// Creating delayed versions of the clock
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clk => _clk-
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_clk => __clk-
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(~d & ~_clk)|(~reset_B)|(~__clk&~_mqi) -> _mqib+
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(d & __clk)|(reset_B & _mqi & _clk) -> _mqib-
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_mqib => _mqi-
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(~_mqi &~__clk)|(~reset_B)|(~_sqi&~_clk) -> _sqib+
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(_mqi &_clk)|(_sqi&__clk&reset_B) -> _sqib-
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_sqib => _sqi-
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_sqib => q-
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}
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}
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}
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}
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