56 lines
2.5 KiB
Verilog
56 lines
2.5 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_33_76_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Ifinal_refresh_d0_d0 , Ifinal_refresh_d0_d1 , Ifinal_refresh_d1_d0 , Ifinal_refresh_d1_d1 , Ifinal_refresh_d2_d0 , Ifinal_refresh_d2_d1 , vdd, vss);
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input vdd;
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input vss;
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input Iin_d0_d0 ;
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input Iin_d0_d1 ;
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input Iin_d1_d0 ;
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input Iin_d1_d1 ;
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input Iin_d2_d0 ;
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input Iin_d2_d1 ;
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// -- signals ---
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wire Iin_d1_d0 ;
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output Iout0 ;
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wire Iin_d2_d1 ;
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output Iout4 ;
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output Ifinal_refresh_d2_d0 ;
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wire Iin_d1_d1 ;
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output Iout2 ;
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output Ifinal_refresh_d0_d0 ;
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output Ifinal_refresh_d1_d1 ;
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output Ifinal_refresh_d1_d0 ;
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wire Iin_d0_d0 ;
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output Iout3 ;
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wire Iin_d2_d0 ;
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wire Iin_d0_d1 ;
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output Iout5 ;
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output Iout1 ;
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output Ifinal_refresh_d2_d1 ;
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output Ifinal_refresh_d0_d1 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree0 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree1 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree2 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree3 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d1 ), .Iin2 (Ifinal_refresh_d2_d0 ), .out(Iout3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree4 (.Iin0 (Ifinal_refresh_d0_d0 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout4 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0andtree_33_4 Iatree5 (.Iin0 (Ifinal_refresh_d0_d1 ), .Iin1 (Ifinal_refresh_d1_d0 ), .Iin2 (Ifinal_refresh_d2_d1 ), .out(Iout5 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_tX0 (.y(Ifinal_refresh_d0_d1 ), .a(Iin_d0_d1 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_tX1 (.y(Ifinal_refresh_d1_d1 ), .a(Iin_d1_d1 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_tX2 (.y(Ifinal_refresh_d2_d1 ), .a(Iin_d2_d1 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_fX0 (.y(Ifinal_refresh_d0_d0 ), .a(Iin_d0_d0 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_fX1 (.y(Ifinal_refresh_d1_d0 ), .a(Iin_d1_d0 ), .vdd(vdd), .vss(vss));
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BUF_X12 Iin_fX2 (.y(Ifinal_refresh_d2_d0 ), .a(Iin_d2_d0 ), .vdd(vdd), .vss(vss));
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endmodule |