65 lines
2.7 KiB
Verilog
65 lines
2.7 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0qdi2bd_35_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_a , Iin_v , Iout_d0 , Iout_d1 , Iout_d2 , Iout_d3 , Iout_d4 , Iout_r , Iout_a , Idly_cfg0 , Idly_cfg1 , Idly_cfg2 , Idly_cfg3 , reset_B, vdd, vss);
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input vdd;
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input vss;
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input Iin_d_d0_d0 ;
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input Iin_d_d0_d1 ;
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input Iin_d_d1_d0 ;
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input Iin_d_d1_d1 ;
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input Iin_d_d2_d0 ;
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input Iin_d_d2_d1 ;
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input Iin_d_d3_d0 ;
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input Iin_d_d3_d1 ;
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input Iin_d_d4_d0 ;
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input Iin_d_d4_d1 ;
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input Iout_a ;
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input Idly_cfg0 ;
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input Idly_cfg1 ;
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input Idly_cfg2 ;
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input Idly_cfg3 ;
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input reset_B;
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// -- signals ---
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wire Iin_d_d0_d0 ;
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output Iout_d4 ;
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wire Iout_vtree_in_d3_d0 ;
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output Iin_a ;
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output Iin_v ;
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wire Iin_d_d3_d1 ;
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wire Iin_d_d2_d1 ;
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output Iout_d1 ;
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wire Iin_d_d2_d0 ;
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wire Iin_d_d1_d1 ;
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wire reset_B;
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wire Iout_vtree_in_d1_d0 ;
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wire Idly_cfg3 ;
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output Iout_d2 ;
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wire Iin_d_d3_d0 ;
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wire Iin_d_d1_d0 ;
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output Iout_r ;
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wire Iout_a ;
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wire Idly_cfg0 ;
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wire Idly_cfg1 ;
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wire Iout_vtree_in_d2_d0 ;
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wire Iin_d_d4_d0 ;
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wire Idly_in ;
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wire Iin_d_d4_d1 ;
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wire Iout_vtree_in_d4_d0 ;
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output Iout_d0 ;
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wire Iin_d_d0_d1 ;
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output Iout_d3 ;
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wire Iout_vtree_in_d0_d0 ;
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wire Idly_cfg2 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly (.out(Iout_r ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0buffer_35_4 Ibuf (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Iout_vtree_in_d0_d0 ), .Iout_d_d0_d1 (Iout_d0 ), .Iout_d_d1_d0 (Iout_vtree_in_d1_d0 ), .Iout_d_d1_d1 (Iout_d1 ), .Iout_d_d2_d0 (Iout_vtree_in_d2_d0 ), .Iout_d_d2_d1 (Iout_d2 ), .Iout_d_d3_d0 (Iout_vtree_in_d3_d0 ), .Iout_d_d3_d1 (Iout_d3 ), .Iout_d_d4_d0 (Iout_vtree_in_d4_d0 ), .Iout_d_d4_d1 (Iout_d4 ), .Iout_a (Iout_a ), .Iout_v (Idly_in ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0vtree_35_4 Iout_vtree (.Iin_d0_d0 (Iout_vtree_in_d0_d0 ), .Iin_d0_d1 (Iout_d0 ), .Iin_d1_d0 (Iout_vtree_in_d1_d0 ), .Iin_d1_d1 (Iout_d1 ), .Iin_d2_d0 (Iout_vtree_in_d2_d0 ), .Iin_d2_d1 (Iout_d2 ), .Iin_d3_d0 (Iout_vtree_in_d3_d0 ), .Iin_d3_d1 (Iout_d3 ), .Iin_d4_d0 (Iout_vtree_in_d4_d0 ), .Iin_d4_d1 (Iout_d4 ), .out(Idly_in ), .vdd(vdd), .vss(vss));
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endmodule |