actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_329_72_72_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0append_329_72_72_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_d_d13_d0 , Iin_d_d13_d1 , Iin_d_d14_d0 , Iin_d_d14_d1 , Iin_d_d15_d0 , Iin_d_d15_d1 , Iin_d_d16_d0 , Iin_d_d16_d1 , Iin_d_d17_d0 , Iin_d_d17_d1 , Iin_d_d18_d0 , Iin_d_d18_d1 , Iin_d_d19_d0 , Iin_d_d19_d1 , Iin_d_d20_d0 , Iin_d_d20_d1 , Iin_d_d21_d0 , Iin_d_d21_d1 , Iin_d_d22_d0 , Iin_d_d22_d1 , Iin_d_d23_d0 , Iin_d_d23_d1 , Iin_d_d24_d0 , Iin_d_d24_d1 , Iin_d_d25_d0 , Iin_d_d25_d1 , Iin_d_d26_d0 , Iin_d_d26_d1 , Iin_d_d27_d0 , Iin_d_d27_d1 , Iin_d_d28_d0 , Iin_d_d28_d1 , Iout_d_d29_d0 , Iout_d_d29_d1 , Iout_d_d30_d0 , Isupply_vss , vdd, vss); 
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   input Iin_d_d7_d0 ;
   input Iin_d_d7_d1 ;
   input Iin_d_d8_d0 ;
   input Iin_d_d8_d1 ;
   input Iin_d_d9_d0 ;
   input Iin_d_d9_d1 ;
   input Iin_d_d10_d0 ;
   input Iin_d_d10_d1 ;
   input Iin_d_d11_d0 ;
   input Iin_d_d11_d1 ;
   input Iin_d_d12_d0 ;
   input Iin_d_d12_d1 ;
   input Iin_d_d13_d0 ;
   input Iin_d_d13_d1 ;
   input Iin_d_d14_d0 ;
   input Iin_d_d14_d1 ;
   input Iin_d_d15_d0 ;
   input Iin_d_d15_d1 ;
   input Iin_d_d16_d0 ;
   input Iin_d_d16_d1 ;
   input Iin_d_d17_d0 ;
   input Iin_d_d17_d1 ;
   input Iin_d_d18_d0 ;
   input Iin_d_d18_d1 ;
   input Iin_d_d19_d0 ;
   input Iin_d_d19_d1 ;
   input Iin_d_d20_d0 ;
   input Iin_d_d20_d1 ;
   input Iin_d_d21_d0 ;
   input Iin_d_d21_d1 ;
   input Iin_d_d22_d0 ;
   input Iin_d_d22_d1 ;
   input Iin_d_d23_d0 ;
   input Iin_d_d23_d1 ;
   input Iin_d_d24_d0 ;
   input Iin_d_d24_d1 ;
   input Iin_d_d25_d0 ;
   input Iin_d_d25_d1 ;
   input Iin_d_d26_d0 ;
   input Iin_d_d26_d1 ;
   input Iin_d_d27_d0 ;
   input Iin_d_d27_d1 ;
   input Iin_d_d28_d0 ;
   input Iin_d_d28_d1 ;
   
   
   
   input Isupply_vss ;

// -- signals ---
   output Iout_d_d29_d0 ;
   wire Iin_d_d18_d1 ;
   wire Iin_d_d9_d1 ;
   wire Iin_d_d18_d0 ;
   wire Iin_d_d26_d1 ;
   wire Iin_d_d20_d1 ;
   wire Iin_d_d16_d0 ;
   wire Iin_d_d2_d0 ;
   wire Iin_d_d0_d0 ;
   wire Iin_d_d11_d1 ;
   wire Iin_d_d6_d0 ;
   wire Iin_d_d1_d1 ;
   wire Iin_d_d0_d1 ;
   wire Iin_d_d2_d1 ;
   wire Iin_d_d27_d1 ;
   wire Iin_d_d15_d0 ;
   wire Iin_d_d10_d1 ;
   wire Iin_d_d6_d1 ;
   wire Iin_d_d4_d1 ;
   wire Iin_d_d3_d1 ;
   wire Iin_d_d27_d0 ;
   wire Iin_d_d13_d0 ;
   wire Iin_d_d28_d1 ;
   wire Iin_d_d15_d1 ;
   wire Iin_d_d3_d0 ;
   wire Iin_d_d13_d1 ;
   wire Iin_d_d1_d0 ;
   wire Iin_d_d28_d0 ;
   wire Iin_d_d19_d1 ;
   wire Iin_d_d20_d0 ;
   wire Iin_d_d16_d1 ;
   wire Iin_d_d23_d0 ;
   wire Iin_d_d19_d0 ;
   wire Iin_d_d10_d0 ;
   wire Iin_d_d5_d1 ;
   output Iout_d_d30_d0 ;
   wire Iin_d_d25_d0 ;
   wire Iin_d_d14_d0 ;
   wire Iin_d_d12_d0 ;
   wire Iin_d_d5_d0 ;
   output Iout_d_d29_d1 ;
   wire Iin_d_d24_d0 ;
   wire Iin_d_d11_d0 ;
   wire Iin_d_d7_d0 ;
   wire Isupply_vss ;
   wire Iin_d_d8_d0 ;
   wire Iin_d_d4_d0 ;
   wire Iin_d_d21_d1 ;
   wire Iin_d_d21_d0 ;
   wire Iin_d_d17_d1 ;
   wire Iin_d_d26_d0 ;
   wire Iin_d_d14_d1 ;
   wire Iin_d_d25_d1 ;
   wire Iin_d_d23_d1 ;
   wire Iin_d_d12_d1 ;
   wire Isb_in ;
   wire Iin_d_d22_d1 ;
   wire Iin_d_d9_d0 ;
   wire Iin_d_d22_d0 ;
   wire Iin_d_d8_d1 ;
   wire Iin_d_d24_d1 ;
   wire Iin_d_d17_d0 ;
   wire Iin_d_d7_d1 ;

// --- instances
TIELO_X1 Itielows0  (.y(Iout_d_d29_d1 ), .vdd(vdd), .vss(vss));
TIELO_X1 Itielows1  (.y(Iout_d_d30_d0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_329_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .Iin_d7_d0 (Iin_d_d7_d0 ), .Iin_d7_d1 (Iin_d_d7_d1 ), .Iin_d8_d0 (Iin_d_d8_d0 ), .Iin_d8_d1 (Iin_d_d8_d1 ), .Iin_d9_d0 (Iin_d_d9_d0 ), .Iin_d9_d1 (Iin_d_d9_d1 ), .Iin_d10_d0 (Iin_d_d10_d0 ), .Iin_d10_d1 (Iin_d_d10_d1 ), .Iin_d11_d0 (Iin_d_d11_d0 ), .Iin_d11_d1 (Iin_d_d11_d1 ), .Iin_d12_d0 (Iin_d_d12_d0 ), .Iin_d12_d1 (Iin_d_d12_d1 ), .Iin_d13_d0 (Iin_d_d13_d0 ), .Iin_d13_d1 (Iin_d_d13_d1 ), .Iin_d14_d0 (Iin_d_d14_d0 ), .Iin_d14_d1 (Iin_d_d14_d1 ), .Iin_d15_d0 (Iin_d_d15_d0 ), .Iin_d15_d1 (Iin_d_d15_d1 ), .Iin_d16_d0 (Iin_d_d16_d0 ), .Iin_d16_d1 (Iin_d_d16_d1 ), .Iin_d17_d0 (Iin_d_d17_d0 ), .Iin_d17_d1 (Iin_d_d17_d1 ), .Iin_d18_d0 (Iin_d_d18_d0 ), .Iin_d18_d1 (Iin_d_d18_d1 ), .Iin_d19_d0 (Iin_d_d19_d0 ), .Iin_d19_d1 (Iin_d_d19_d1 ), .Iin_d20_d0 (Iin_d_d20_d0 ), .Iin_d20_d1 (Iin_d_d20_d1 ), .Iin_d21_d0 (Iin_d_d21_d0 ), .Iin_d21_d1 (Iin_d_d21_d1 ), .Iin_d22_d0 (Iin_d_d22_d0 ), .Iin_d22_d1 (Iin_d_d22_d1 ), .Iin_d23_d0 (Iin_d_d23_d0 ), .Iin_d23_d1 (Iin_d_d23_d1 ), .Iin_d24_d0 (Iin_d_d24_d0 ), .Iin_d24_d1 (Iin_d_d24_d1 ), .Iin_d25_d0 (Iin_d_d25_d0 ), .Iin_d25_d1 (Iin_d_d25_d1 ), .Iin_d26_d0 (Iin_d_d26_d0 ), .Iin_d26_d1 (Iin_d_d26_d1 ), .Iin_d27_d0 (Iin_d_d27_d0 ), .Iin_d27_d1 (Iin_d_d27_d1 ), .Iin_d28_d0 (Iin_d_d28_d0 ), .Iin_d28_d1 (Iin_d_d28_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_32_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d29_d0 ), .vdd(vdd), .vss(vss));
endmodule