511 lines
21 KiB
Plaintext
511 lines
21 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/registers.act";
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/interfaces.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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export template<pint N_IN, // Size of input data from outside world
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
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N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
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N_BUFFERS,
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N_LINE_PD_DLY, // Number of dummy delays to add line pull down
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REG_NCA, REG_NCW, REG_M>
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defproc texel_core (avMx1of2<N_IN> in, out;
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Mx1of2<REG_NCW> reg_data[REG_M];
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// Dummy synapses and neurons in the handshake blocks
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// should be removed pre-innovus, else they are floating.
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// a1of1 synapses[N_SYN_X * N_SYN_Y];
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// a1of1 neurons[N_NRN_X * N_NRN_Y];
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// Synapse decoder stuff
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// The analogue core and connects to these to replace the above synapses.
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bool! dec_req_x[N_SYN_X], dec_req_y[N_SYN_Y];
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bool? dec_ackB[N_SYN_X];
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a1of1 syn_pu[N_SYN_X];
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// Neuron encoder stuff
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a1of1 enc_inx[N_NRN_X], enc_iny[N_NRN_Y];
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a1of1 nrn_pd_x[N_NRN_X], nrn_pd_y[N_NRN_Y];
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// Monitors and flags to/from core, and selected mon out.
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bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
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bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
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bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
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power supply;
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bool? reset_B, reset_reg_B){
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bool _reset_BX;
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BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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pint index = 0; // Just useful
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// Onwards
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fifo<N_IN,N_BUFFERS> fifo_in(.in = in, .reset_B = _reset_BX, .supply = supply);
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demux_bit_msb<N_IN-1> _demux(.in = fifo_in.out, .reset_B = _reset_BX, .supply = supply);
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// Register
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = _reset_BX, .supply = supply);
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register_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
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.supply = supply, .reset_B = reset_reg_B);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out, .reset_B = _reset_BX, .supply = supply);
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// Spike Decoder
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pint NC_SYN;
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NC_SYN = NC_SYN_X + NC_SYN_Y;
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
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.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
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.out_req_x = dec_req_x, .out_req_y = dec_req_y,
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.to_pu = syn_pu,
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.in_ackB_decoder = dec_ackB,
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.supply = supply, .reset_B = _reset_BX);
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INV_X1 dly_cfg_inverters[N_SYN_DLY_CFG];
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(i:N_SYN_DLY_CFG:
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dly_cfg_inverters[i].a = register.data[0].d[1+i].t; // iff t is high, is the delay disabled.
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dly_cfg_inverters[i].vdd = supply.vdd;
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dly_cfg_inverters[i].vss = supply.vss;
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decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
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)
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// Synapse handshake circuits, to be removed for innovus
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// decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
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// .synapses = synapses,
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// .in_req_x = dec_req_x, .in_req_y = dec_req_y,
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// .to_pu = syn_pu,
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// .out_ackB_decoder = dec_ackB,
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// .supply = supply);
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// Neurons + encoder
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pint NC_NRN;
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NC_NRN = NC_NRN_X + NC_NRN_Y;
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encoder2d_simple<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, N_LINE_PD_DLY> encoder(
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.inx = enc_inx, .iny = enc_iny,
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.reset_B = _reset_BX, .supply = supply,
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.to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y);
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fifo<NC_NRN, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
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.reset_B = _reset_BX, .supply = supply);
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// Neuron handshake circuits, to be removed for innovus
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// nrn_hs_2d_array<N_NRN_X,N_NRN_Y> nrn_grid(.in = neurons,
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// .outx = enc_inx, .outy = enc_iny,
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// .to_pd_x = nrn_pd_x, .to_pd_y = nrn_pd_y,
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// .supply = supply, .reset_B = _reset_BX);
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// Merge
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append<NC_NRN, N_IN-NC_NRN, 0> append_enc(.in = fifo_enc2mrg.out, .supply = supply);
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append<N_IN-2, 2, 2> append_reg(.in = fifo_reg2mrg.out, .supply = supply);
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merge<N_IN> merge_enc8reg(.in1 = append_enc.out, .in2 = append_reg.out,
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.supply = supply, .reset_B = _reset_BX);
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// Output
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fifo<N_IN, N_BUFFERS> fifo_out(.in = merge_enc8reg.out, .out = out,
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.reset_B = _reset_BX, .supply = supply);
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// Neuron/synapse monitor targeters
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pint NC_NRN_MON_X = std::ceil_log2(N_NRN_MON_X);
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pint NC_NRN_MON_Y = std::ceil_log2(N_NRN_MON_Y);
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pint NC_SYN_MON_X = std::ceil_log2(N_SYN_MON_X);
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pint NC_SYN_MON_Y = std::ceil_log2(N_SYN_MON_Y);
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decoder_dualrail_en<NC_NRN_MON_X, N_NRN_MON_X> nrn_mon_dec_x(.supply = supply);
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nrn_mon_dec_x.en = register.data[1].d[0].t;
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(i:NC_NRN_MON_X:
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nrn_mon_dec_x.in.d[i] = register.data[2].d[i];
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)
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sigbuf_boolarray<N_NRN_MON_X, 13> nrn_mon_x_buf(.in = nrn_mon_dec_x.out, .out = nrn_mon_x, .supply = supply);
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decoder_dualrail_en<NC_NRN_MON_Y, N_NRN_MON_Y> nrn_mon_dec_y(.supply = supply);
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nrn_mon_dec_y.en = register.data[1].d[0].t;
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(i:NC_NRN_MON_Y:
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nrn_mon_dec_y.in.d[i] = register.data[2].d[i+NC_NRN_MON_X];
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)
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sigbuf_boolarray<N_NRN_MON_Y, 48> nrn_mon_y_buf(.in = nrn_mon_dec_y.out, .out = nrn_mon_y, .supply = supply);
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decoder_dualrail_en<NC_SYN_MON_X, N_SYN_MON_X> syn_mon_dec_x(
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.supply = supply);
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syn_mon_dec_x.en = register.data[1].d[1].t;
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(i:NC_SYN_MON_X:
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syn_mon_dec_x.in.d[i] = register.data[3].d[i];
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)
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sigbuf_boolarray<N_SYN_MON_X, 13> syn_mon_x_buf(.out = syn_mon_x, .supply = supply);
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decoder_dualrail_en<NC_SYN_MON_Y, N_SYN_MON_Y> syn_mon_dec_y(.supply = supply);
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syn_mon_dec_y.en = register.data[1].d[1].t;
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(i:NC_SYN_MON_Y:
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syn_mon_dec_y.in.d[i] = register.data[3].d[i+NC_SYN_MON_X];
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)
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sigbuf_boolarray<N_SYN_MON_Y, 48> syn_mon_y_buf(.out = syn_mon_y, .in = syn_mon_dec_y.out, .supply = supply);
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// Device debug hard-wired safety (reg0, b05 = DEV_DEBUG)
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// Stops the possibility of dev_mon being high while some other sig is high.
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// Otherwise boom.
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bool DEV_DEBUG;
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pint NSMX4 = N_SYN_MON_X/4; // Self explanatory
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sigbuf<std::max(NSMX4,4)> sb_DEV_DEBUG(.in = register.data[0].d[5].t,
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.supply = supply);
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DEV_DEBUG = sb_DEV_DEBUG.out[0];
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[NSMX4 >= 1 ->
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AND2_X1 ands_devmon[NSMX4];
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(i:NSMX4:
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ands_devmon[i].a = syn_mon_dec_x.out[1+i*4];
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ands_devmon[i].b = DEV_DEBUG;
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ands_devmon[i].y = syn_mon_x_buf.in[1+i*4];
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ands_devmon[i].vdd = supply.vdd;
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ands_devmon[i].vss = supply.vss;
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)
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// Wire up the non-ANDed lines.
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(i:N_SYN_MON_X:
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[~(i%4 = 1) ->
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syn_mon_x_buf.in[i] = syn_mon_dec_x.out[i];
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]
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)
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]
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// Create TBUFs for each synapse column,
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// ctrl wired to mon line (first in each 4).
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TBUF_X4 syn_x_AMZI_tbuf[N_SYN_X * N_MON_AMZO_PER_SYN];
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sigbuf_boolarray<N_MON_AMZO_PER_SYN, 40> syn_mon_AMZO_sb(.out = syn_mon_AMZO, .supply = supply);
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(j:N_MON_AMZO_PER_SYN:
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(i:N_SYN_X:
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index = i*N_MON_AMZO_PER_SYN + j;
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syn_x_AMZI_tbuf[index].a = syn_mon_AMZI[index];
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syn_x_AMZI_tbuf[index].en = syn_mon_x[i*4];
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syn_x_AMZI_tbuf[index].y = syn_mon_AMZO_sb.in[j];
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)
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)
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// Create TBUFs for each neuron column,
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// ctrl wired to mon line (first in each 4).
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TBUF_X4 nrn_x_AMZI_tbuf[N_NRN_X * N_MON_AMZO_PER_NRN];
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sigbuf_boolarray<N_MON_AMZO_PER_NRN, 40> nrn_mon_AMZO_sb(.out = nrn_mon_AMZO, .supply = supply);
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(j:N_MON_AMZO_PER_NRN:
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(i:N_NRN_X:
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index = i*N_MON_AMZO_PER_NRN + j;
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nrn_x_AMZI_tbuf[index].a = nrn_mon_AMZI[index];
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nrn_x_AMZI_tbuf[index].en = nrn_mon_x[i*2];
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nrn_x_AMZI_tbuf[index].y = nrn_mon_AMZO_sb.in[j];
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)
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)
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// Create NON buffered signals from register to nrns.
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(i:N_FLAGS_PER_NRN:
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nrn_flags_EFO[i] = register.data[5].d[i].t;
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)
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// Create NON buffered signals from register to synapses.
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// Includes safety on the first 3 flags with dev mon.
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(i:3..N_FLAGS_PER_SYN-1:
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syn_flags_EFO[i] = register.data[4].d[i].t;
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)
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AND2_X1 syn_flags_dev_safety[3];
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BUF_X4 syn_flags_dev_safety_sb[3];
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(i:0..2:
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syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
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syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
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syn_flags_dev_safety_sb[i].a = syn_flags_dev_safety[i].y;
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syn_flags_dev_safety_sb[i].y = syn_flags_EFO[i];
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syn_flags_dev_safety[i].vdd = supply.vdd;
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syn_flags_dev_safety[i].vss = supply.vss;
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syn_flags_dev_safety_sb[i].vdd = supply.vdd;
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syn_flags_dev_safety_sb[i].vss = supply.vss;
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)
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}
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export template<pint N_IN, // Size of input data from outside world
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
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N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
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N_BUFFERS,
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N_LINE_PD_DLY, // Number of dummy delays to add line pull down
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N_BD_DLY_CFG, N_BD_DLY_CFG2,
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REG_NCA, REG_NCW, REG_M>
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defproc texel_singlecore (bd<N_IN> in, out;
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Mx1of2<REG_NCW> reg_data[REG_M];
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// a1of1 synapses[N_SYN_X * N_SYN_Y];
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// a1of1 neurons[N_NRN_X * N_NRN_Y];
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bool! nrn_mon_x[N_NRN_MON_X], nrn_mon_y[N_NRN_MON_Y];
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bool! syn_mon_x[N_SYN_MON_X], syn_mon_y[N_SYN_MON_Y];
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bool? syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! syn_mon_AMZO[N_MON_AMZO_PER_SYN], nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! syn_flags_EFO[N_FLAGS_PER_SYN], nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? loopback_en;
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power supply;
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bool? reset_B){
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bool _reset_BX;
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BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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pint index = 0; // Just useful
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bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
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.reset_B = _reset_BX, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
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// Loopback
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
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dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
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.supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
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// Onwards to core
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fifo<N_IN,N_BUFFERS> fifo_fork2core(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
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texel_core<N_IN,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
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core(.in = fifo_fork2core.out,
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.reg_data = reg_data,
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// .synapses = synapses,
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// .neurons = neurons,
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.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
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.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
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.syn_mon_AMZI = syn_mon_AMZI, .nrn_mon_AMZI = nrn_mon_AMZI,
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.syn_mon_AMZO = syn_mon_AMZO, .nrn_mon_AMZO = nrn_mon_AMZO,
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.syn_flags_EFO = syn_flags_EFO, .nrn_flags_EFO = nrn_flags_EFO,
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.reset_B = _reset_BX,
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.supply = supply
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);
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// qdi2bd
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fifo<N_IN, N_BUFFERS> fifo_core2mrg(.in = core.out,
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.reset_B = _reset_BX, .supply = supply);
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// merge core output and loopback
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merge<N_IN> merge_drop8core(.in1 = fifo_core2mrg.out, .in2 = fifo_drop2mrg.out,
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.supply = supply, .reset_B = _reset_BX);
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qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = merge_drop8core.out, .out = out, .dly_cfg = bd_dly_cfg,
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.reset_B = _reset_BX, .supply = supply);
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}
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export template<pint N_IN, // Size of input data from outside world
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN, // Number of signals that each synapse outputs to be monitored.
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N_FLAGS_PER_SYN, N_FLAGS_PER_NRN, // Number of signals that each nrn/syn recieves from the register.
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N_BUFFERS,
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N_LINE_PD_DLY, // Number of dummy delays to add line pull down
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N_BD_DLY_CFG, N_BD_DLY_CFG2,
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REG_NCA, REG_NCW, REG_M>
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defproc texel_dualcore (bd<N_IN> in, out;
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Mx1of2<REG_NCW> c1_reg_data[REG_M];
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// a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
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// a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
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bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
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bool? c1_dec_ackB[N_SYN_X];
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a1of1 c1_syn_pu[N_SYN_X];
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a1of1 c1_enc_inx[N_NRN_X], c1_enc_iny[N_NRN_Y];
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a1of1 c1_nrn_pd_x[N_NRN_X], c1_nrn_pd_y[N_NRN_Y];
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bool! c1_nrn_mon_x[N_NRN_MON_X], c1_nrn_mon_y[N_NRN_MON_Y];
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bool! c1_syn_mon_x[N_SYN_MON_X], c1_syn_mon_y[N_SYN_MON_Y];
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bool? c1_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
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Mx1of2<REG_NCW> c2_reg_data[REG_M];
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// a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
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// a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
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bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
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bool? c2_dec_ackB[N_SYN_X];
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a1of1 c2_syn_pu[N_SYN_X];
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a1of1 c2_enc_inx[N_NRN_X], c2_enc_iny[N_NRN_Y];
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a1of1 c2_nrn_pd_x[N_NRN_X], c2_nrn_pd_y[N_NRN_Y];
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bool! c2_nrn_mon_x[N_NRN_MON_X], c2_nrn_mon_y[N_NRN_MON_Y];
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bool! c2_syn_mon_x[N_SYN_MON_X], c2_syn_mon_y[N_SYN_MON_Y];
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bool? c2_syn_mon_AMZI[N_SYN_X * N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZI[N_NRN_X * N_MON_AMZO_PER_NRN];
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bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
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bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
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bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
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bool? loopback_en;
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power supply;
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bool? reset_B, reset_reg_B){
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// Reset buffers
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bool _reset_BX;
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BUF_X12 reset_buf(.a = reset_B, .y = _reset_BX, .vdd = supply.vdd, .vss = supply.vss);
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bd2qdi<N_IN, N_BD_DLY_CFG, N_BD_DLY_CFG2> _bd2qdi(.in = in, .dly_cfg = bd_dly_cfg, .dly_cfg2 = bd_dly_cfg2,
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.reset_B = _reset_BX, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = _reset_BX, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = _reset_BX, .supply = supply);
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// Loopback
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = _reset_BX, .supply = supply);
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dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
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.supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_drop2mrg(.in = _loopback_dropper.out, .reset_B = _reset_BX, .supply = supply);
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// Onwards to core demux
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fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = _reset_BX, .supply = supply);
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demux_bit_msb<N_IN-1> core_dmx(.in = fifo_fork2dmx.out, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2core1(.in = core_dmx.out1, .reset_B = _reset_BX, .supply = supply);
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2core2(.in = core_dmx.out2, .reset_B = _reset_BX, .supply = supply);
|
|
|
|
// Cores
|
|
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
|
|
core1(.in = fifo_dmx2core1.out,
|
|
|
|
.reg_data = c1_reg_data,
|
|
// .synapses = c1_synapses,
|
|
// .neurons = c1_neurons,
|
|
|
|
.dec_req_x = c1_dec_req_x, .dec_req_y = c1_dec_req_y,
|
|
.dec_ackB = c1_dec_ackB,
|
|
.syn_pu = c1_syn_pu,
|
|
|
|
.enc_inx = c1_enc_inx, .enc_iny = c1_enc_iny,
|
|
.nrn_pd_x = c1_nrn_pd_x, .nrn_pd_y = c1_nrn_pd_y,
|
|
|
|
.nrn_mon_x = c1_nrn_mon_x, .nrn_mon_y = c1_nrn_mon_y,
|
|
.syn_mon_x = c1_syn_mon_x, .syn_mon_y = c1_syn_mon_y,
|
|
.syn_mon_AMZI = c1_syn_mon_AMZI, .nrn_mon_AMZI = c1_nrn_mon_AMZI,
|
|
.syn_mon_AMZO = c1_syn_mon_AMZO, .nrn_mon_AMZO = c1_nrn_mon_AMZO,
|
|
.syn_flags_EFO = c1_syn_flags_EFO, .nrn_flags_EFO = c1_nrn_flags_EFO,
|
|
|
|
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
|
|
.supply = supply
|
|
);
|
|
|
|
|
|
texel_core<N_IN-1,N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,N_SYN_DLY_CFG,N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,N_MON_AMZO_PER_SYN, N_MON_AMZO_PER_NRN,N_FLAGS_PER_SYN, N_FLAGS_PER_NRN,N_BUFFERS,N_LINE_PD_DLY, REG_NCA, REG_NCW, REG_M>
|
|
core2(.in = fifo_dmx2core2.out,
|
|
|
|
.reg_data = c2_reg_data,
|
|
// .synapses = c2_synapses,
|
|
// .neurons = c2_neurons,
|
|
|
|
.dec_req_x = c2_dec_req_x, .dec_req_y = c2_dec_req_y,
|
|
.dec_ackB = c2_dec_ackB,
|
|
.syn_pu = c2_syn_pu,
|
|
|
|
.enc_inx = c2_enc_inx, .enc_iny = c2_enc_iny,
|
|
.nrn_pd_x = c2_nrn_pd_x, .nrn_pd_y = c2_nrn_pd_y,
|
|
|
|
.nrn_mon_x = c2_nrn_mon_x, .nrn_mon_y = c2_nrn_mon_y,
|
|
.syn_mon_x = c2_syn_mon_x, .syn_mon_y = c2_syn_mon_y,
|
|
.syn_mon_AMZI = c2_syn_mon_AMZI, .nrn_mon_AMZI = c2_nrn_mon_AMZI,
|
|
.syn_mon_AMZO = c2_syn_mon_AMZO, .nrn_mon_AMZO = c2_nrn_mon_AMZO,
|
|
.syn_flags_EFO = c2_syn_flags_EFO, .nrn_flags_EFO = c2_nrn_flags_EFO,
|
|
|
|
.reset_B = _reset_BX, .reset_reg_B = reset_reg_B,
|
|
.supply = supply
|
|
);
|
|
|
|
fifo<N_IN-1,N_BUFFERS> fifo_core1out(.in = core1.out, .reset_B = _reset_BX, .supply = supply);
|
|
fifo<N_IN-1,N_BUFFERS> fifo_core2out(.in = core2.out, .reset_B = _reset_BX, .supply = supply);
|
|
|
|
|
|
// Merge cores
|
|
append<N_IN-1, 1, 0> append_core1(.in = fifo_core1out.out, .supply = supply);
|
|
append<N_IN-1, 1, 1> append_core2(.in = fifo_core2out.out, .supply = supply);
|
|
merge<N_IN> merge_core1x2(.in1 = append_core1.out, .in2 = append_core2.out,
|
|
.supply = supply, .reset_B = _reset_BX);
|
|
|
|
// Merge cores and loopback
|
|
merge<N_IN> merge_drop8core(.in1 = merge_core1x2.out, .in2 = fifo_drop2mrg.out,
|
|
.reset_B = _reset_BX, .supply = supply);
|
|
|
|
// qdi2bd
|
|
fifo<N_IN, N_BUFFERS> fifo_mrg2bd(.in = merge_drop8core.out,
|
|
.reset_B = _reset_BX, .supply = supply);
|
|
qdi2bd<N_IN, N_BD_DLY_CFG> _qdi2bd(.in = fifo_mrg2bd.out, .out = out, .dly_cfg = bd_dly_cfg,
|
|
.reset_B = _reset_BX, .supply = supply);
|
|
|
|
}
|
|
|
|
}
|
|
}
|
|
|