94 lines
3.0 KiB
Plaintext
94 lines
3.0 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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/**
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* Creates a synapse-neuron dummy block,
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* where any synapse being triggered makes the neuron "spike".
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*/
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export template<pint N_SYN>
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defproc dummy_neuron_block (a1of1 synapses[N_SYN], neuron; power supply){
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// OR over reqs from syn in to neuron out
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ortree<N_SYN> _ortree(.out = neuron.r, .supply = supply);
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(i:N_SYN: _ortree.in[i] = synapses[i].r;)
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// ANDs piping the ack back to the proper synapse
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BUF_X12 nrn_ack_buf(.a = neuron.a, .vdd = supply.vdd, .vss = supply.vss);
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AND2_X1 ands[N_SYN];
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(i:N_SYN:
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ands[i].a = nrn_ack_buf.y;
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ands[i].b = synapses[i].r;
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ands[i].y = synapses[i].a;
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ands[i].vss = supply.vss;
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ands[i].vdd = supply.vdd;
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)
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}
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/**
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* Create an array of neuron dummy blocks.
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* Note that this is custom made for the indexing on the texel chip.
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* And so should be reused *with care*.
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*/
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export template<pint N_SYN_PER_NRN, N_NRN, N_NRN_X>
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defproc dummy_neuron_core (a1of1 synapses[N_SYN_PER_NRN * N_NRN], neurons[N_NRN]; power supply){
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dummy_neuron_block<N_SYN_PER_NRN> blocks[N_NRN];
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pint Xn, Yn, Xs, Ys;
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(i:N_NRN:
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Yn = i/N_NRN_X;
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Xn = i-Yn*N_NRN_X;
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neurons[i] = blocks[i].neuron;
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blocks[i].supply = supply;
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(j:N_SYN_PER_NRN: // moron, need to think about neuron indexxing too
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Xs = Xn;
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Ys = Yn*N_SYN_PER_NRN + j;
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blocks[i].synapses[j] = synapses[Ys*N_NRN_X + Xs];
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)
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)
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}
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}
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} |