67 lines
2.2 KiB
Plaintext
67 lines
2.2 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/registers.act";
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/interfaces.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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export
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defproc sadc_hs (a1of1 in, out; bool? reset_B; power supply) {
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bool _en;
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bool _out_a_B;
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INV_X1 ack_inv(.a = out.a, .y = _out_a_B, .vdd = supply.vdd, .vss = supply.vss);
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A_2C1N_RB_X1 A_ack(.c1 = _en, .c2 = in.r, .n1 = out.r, .y = in.a,
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.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
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A_2C1N_RB_X1 A_req(.c1 = _en, .c2 = _out_a_B, .n1 = in.r, .y = out.r,
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.pr_B = reset_B, .sr_B = reset_B, .vss = supply.vss, .vdd = supply.vdd);
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A_1C1P_X1 A_en(.c1 = in.a, .p1 = out.r, .y = _en,
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.vdd = supply.vdd, .vss = supply.vss);
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}
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}
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}
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