353 lines
9.3 KiB
Plaintext
353 lines
9.3 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/coders.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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/**
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* A single register made out of A cells.
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* MSB is whether to read or write.
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* Currently only handles writing.
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* NOTE: this does not handle in.v properly, and instead has in.v = in.a
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*/
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//@TODO Get rid of scarying warning
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export template<pint N>
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defproc register_acells_improved(avMx1of2<N+1> in; Mx1of2<N> out;
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bool? reset_B; power supply) {
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bool _resetX[N], _reset_BX[N];
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bool _en, _enBX;
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bool _flush, _flushBX;
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bool _out_v, _out_vB;
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bool _w = in.d.d[N].t;
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INV_X2 out_val_inv(.a = _out_v, .y = _out_vB,
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.vdd = supply.vdd, .vss= supply.vss);
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// Reset sigs
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INV_X1 reset_inv(.a = reset_B, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N> reset_sb(.in = reset_inv.y, .out = _resetX, .supply = supply);
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sigbuf<N> resetB_sb(.in=reset_B, .out=_reset_BX, .supply = supply);
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A_2C1N_RB_X1 A_flush(.c1 = _en, .c2 = _out_v, .n1 = _w, .y = _flush,
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.vdd = supply.vdd, .vss = supply.vss, .pr_B = _reset_BX[0], .sr_B = _reset_BX[0]);
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A_2C_X1 A_en(.c1 = _w, .c2 = _out_vB, .y = _en,
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.vdd = supply.vdd, .vss = supply.vss);
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INV_X1 flush_inv(.a = _flush, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N*2> sb_flushB(.in = flush_inv.y, .supply = supply);
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sb_flushB.out[0] = _flushBX;
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INV_X1 en_inv(.a = _en, .vdd = supply.vdd, .vss = supply.vss);
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sigbuf<N*2> sb_enB(.in = en_inv.y, .supply = supply);
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sb_enB.out[0] = _enBX;
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vtree<N> vc(.in = out, .out = _out_v, .supply = supply);
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// WARNING WARNING
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in.v = in.a;
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A_1C1P_X1 A_ack(.c1 = _en, .p1 = _out_vB, .y = in.a,
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.vdd = supply.vdd, .vss = supply.vss);
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//function
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A_2C1N_SB_X4 f_buf_func[N];
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A_2C1N_RB_X4 t_buf_func[N];
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(i:N:
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f_buf_func[i].y=out.d[i].f;
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t_buf_func[i].y=out.d[i].t;
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f_buf_func[i].c1=_flushBX;
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t_buf_func[i].c1=_flushBX;
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f_buf_func[i].c2=_enBX;
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t_buf_func[i].c2=_enBX;
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f_buf_func[i].n1=in.d.d[i].f;
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t_buf_func[i].n1=in.d.d[i].t;
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f_buf_func[i].vdd=supply.vdd;
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t_buf_func[i].vdd=supply.vdd;
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f_buf_func[i].vss=supply.vss;
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t_buf_func[i].vss=supply.vss;
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f_buf_func[i].pr = _resetX[i];
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f_buf_func[i].sr = _resetX[i];
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t_buf_func[i].pr_B = _reset_BX[i];
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t_buf_func[i].sr_B = _reset_BX[i];
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)
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}
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/**
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* Array of registers made out of A-cells
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* params:
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* NcW: number of bits in Words to be stored in buffers
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* NcA: number of bits in Address
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* M: number of registers. M = 2^Nc_addr would be a natural choice.
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* Input packets should be
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* [-addr-][-word-][r/w]
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*/
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export template<pint NcA, NcW, M>
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defproc register_wr_array(avMx1of2<NcA + NcW + 1> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
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bool? reset_B; power supply) {
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// Input valid tree
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vtree<NcA + NcW + 1> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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decoder.in.d[i] = in.d.d[i];
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)
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// OrTree over acks from all registers
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ortree<M> ack_ortree(.supply = supply);
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bool _write_ack;
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// C element handling in ack
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A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
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.vss = supply.vss, .vdd = supply.vdd);
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// Bit to join the acks either from read or write
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bool _read_ack;
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_read_ack = out.a;
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OR2_X1 ack_rw_or(.a = _read_ack, .b = _write_ack,
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.vdd = supply.vdd, .vss = supply.vss);
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A_2C_B_X1 ack_safety(.c1 = ack_rw_or.y, .c2 = in.v, .y = in.a);
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// Write bit selector
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bool _w = in.d.d[NcA+NcW].t;
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bool _wX[M];
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sigbuf<M> _w_sb(.in = _w, .out = _wX, .supply = supply);
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A_2C_B_X1 write_selectors[M];
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(i:M:
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write_selectors[i].c1 = _wX[i];
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write_selectors[i].c2 = decoder.out[i];
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write_selectors[i].vdd = supply.vdd;
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write_selectors[i].vss = supply.vss;
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)
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// Registers
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register_acells_improved<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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(j:NcW:
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registers[i].in.d.d[j] = in.d.d[j + NcA];
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)
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// Connect the (selected) write bit
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registers[i].in.d.d[NcW].t = write_selectors[i].y;
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tielow_writebit_f[i].vdd = supply.vdd;
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tielow_writebit_f[i].vss = supply.vss;
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registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// Connect to ack ortree
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registers[i].in.a = ack_ortree.in[i];
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// Connect outputs
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data[i] = registers[i].out;
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registers[i].supply = supply;
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registers[i].reset_B = reset_B;
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)
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// Read bit selector
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bool _r = in.d.d[NcA+NcW].f;
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bool _rX[M+NcA];
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sigbuf<M+NcA> _r_sb(.in = _r, .out = _rX, .supply = supply);
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A_2C_B_X1 read_selectors[M];
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sigbuf_boolarray<M, NcW*2> read_selectorsX(.supply = supply);
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(i:M:
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read_selectors[i].c1 = _rX[i];
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read_selectors[i].c2 = decoder.out[i];
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read_selectors[i].vdd = supply.vdd;
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read_selectors[i].vss = supply.vss;
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read_selectorsX.in[i] = read_selectors[i].y;
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)
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// OrTrees for each output word bit on read
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ortree<M> out_ortrees_t[NcW];
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ortree<M> out_ortrees_f[NcW];
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(i:NcW:
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out_ortrees_t[i].out = out.d.d[i+NcA].t;
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out_ortrees_f[i].out = out.d.d[i+NcA].f;
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out_ortrees_t[i].supply = supply;
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out_ortrees_f[i].supply = supply;
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)
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// ANDs over each reg's data
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// and whether it is selected for read.
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AND2_X1 and_reads_t[NcW * M];
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AND2_X1 and_reads_f[NcW * M];
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pint index;
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(i:NcW:
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(j:M:
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index = i + j*NcW;
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and_reads_t[index].a = data[j].d[i].t;
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and_reads_t[index].b = read_selectorsX.out[j];
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and_reads_f[index].a = data[j].d[i].f;
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and_reads_f[index].b = read_selectorsX.out[j];
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and_reads_t[index].y = out_ortrees_t[i].in[j];
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and_reads_f[index].y = out_ortrees_f[i].in[j];
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and_reads_t[index].vss = supply.vss;
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and_reads_t[index].vdd = supply.vdd;
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and_reads_f[index].vss = supply.vss;
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and_reads_f[index].vdd = supply.vdd;
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)
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)
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// C elements passing address to out on read.
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A_2C_B_X1 addr_read_t[NcA];
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A_2C_B_X1 addr_read_f[NcA];
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(i:NcA:
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addr_read_t[i].c1 = in.d.d[i].t;
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addr_read_f[i].c1 = in.d.d[i].f;
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addr_read_t[i].c2 = _rX[M+i];
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addr_read_f[i].c2 = _rX[M+i];
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addr_read_t[i].y = out.d.d[i].t;
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addr_read_f[i].y = out.d.d[i].f;
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addr_read_t[i].vdd = supply.vdd;
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addr_read_t[i].vss = supply.vss;
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addr_read_f[i].vdd = supply.vdd;
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addr_read_f[i].vss = supply.vss;
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)
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}
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/**
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* Array of registers made out of A-cells.
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* !!!Registers ONLY have write functionality!!!
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* params:
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* NcW: number of bits in Words to be stored in buffers
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* NcA: number of bits in Address
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* M: number of registers. M = 2^Nc_addr would be a natural choice.
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* Input packets should be
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* LSB [-addr-][-word-] MSB
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*/
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//@TODO check if it is used
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export template<pint NcA, NcW, M>
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defproc register_w_array(avMx1of2<NcA + NcW> in; Mx1of2<NcW> data[M]; avMx1of2<NcA+NcW> out;
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bool? reset_B; power supply) {
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// Input valid tree
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vtree<NcA + NcW> input_valid(.in = in.d, .out = in.v,
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.supply = supply);
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// Address decoder
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decoder_dualrail<NcA, M> decoder(.supply = supply);
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(i:NcA:
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decoder.in.d[i] = in.d.d[i];
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)
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// OrTree over acks from all registers
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ortree<M> ack_ortree(.supply = supply);
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bool _write_ack;
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// C element handling in ack
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A_2C_B_X1 in_ack_Cel(.c1 = ack_ortree.out, .c2 = input_valid.out, .y = _write_ack,
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.vss = supply.vss, .vdd = supply.vdd);
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A_2C_B_X1 ack_safety(.c1 = _write_ack, .c2 = in.v, .y = in.a);
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// Registers
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register_acells_improved<NcW> registers[M];
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TIELO_X1 tielow_writebit_f[M];
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(i:M:
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// Connect each register to word inputs.
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(j:NcW:
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registers[i].in.d.d[j] = in.d.d[j + NcA];
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)
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// Connect the (selected) write bit
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registers[i].in.d.d[NcW].t = decoder.out[i];
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tielow_writebit_f[i].vdd = supply.vdd;
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tielow_writebit_f[i].vss = supply.vss;
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registers[i].in.d.d[NcW].f = tielow_writebit_f[i].y;
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// Connect to ack ortree
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registers[i].in.a = ack_ortree.in[i];
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// Connect outputs
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data[i] = registers[i].out;
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registers[i].supply = supply;
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registers[i].reset_B = reset_B;
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)
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}
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}}
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