152 lines
5.5 KiB
Plaintext
152 lines
5.5 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/coders.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
|
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/registers.act";
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import "../../dataflow_neuro/coders.act";
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// import tmpl::dataflow_neuro;
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// import tmpl::dataflow_neuro;
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import std::channel;
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open std::channel;
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namespace tmpl {
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namespace dataflow_neuro {
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export template<N_IN, // Size of input data from outside world
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y, // Number of neurons / synapses
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_BUFFERS,
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N_LINE_PD_DLY, // Number of dummy delays to add line pull down
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N_BD_DLY_CFG,
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REG_NCA, REG_NCW, REG_M>
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defproc chip_texel (bd<N_IN> in, out;
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Mx1of2<REG_NCW> reg_data[REG_M];
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a1of1 synapses[N_SYN_X * N_SYN_Y];
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a1of1 neurons[N_NRN_X * N_NRN_Y];
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bool? bd_dly_cfg[N_BD_DLY_CFG];
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bool? loopback_en;
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power supply;
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bool? reset_B){
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bd2qdi<N_IN, N_BD_DLY_CFG> _bd2qdi(.in = in, .supply = supply);
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fifo<N_IN,N_BUFFERS> fifo_in2fork(.in = _bd2qdi.out, .reset_B = reset_B, .supply = supply);
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fork<N_IN> _fork(.in = fifo_in2fork.out, .reset_B = reset_B, .supply = supply);
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// Loopback
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fifo<N_IN,N_BUFFERS> fifo_fork2drop(.in = _fork.out1, .reset_B = reset_B, .supply = supply);
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dropper_static<N_IN, false> _loopback_dropper(.in = fifo_fork2drop.out, .cond = loopback_en,
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.supply = supply);
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// Onwards
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fifo<N_IN,N_BUFFERS> fifo_fork2dmx(.in = _fork.out2, .reset_B = reset_B, .supply = supply);
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demux_msb<N_IN-1> _demux(.in = fifo_fork2dmx.out, .reset_B = reset_B, .supply = supply);
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// Register
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2reg(.in = _demux.out2, .reset_B = reset_B, .supply = supply);
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registerA_wr_array<REG_NCA, REG_NCW, REG_M> register(.in = fifo_dmx2reg.out, .data = reg_data,
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.supply = supply, .reset_B = reset_B);
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fifo<N_IN-2,N_BUFFERS> fifo_reg2mrg(.in = register.out)
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// TO ADD: nrn/syn mon decoders
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// Decoder
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// slice_data<N_IN-1>
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fifo<N_IN-1,N_BUFFERS> fifo_dmx2dec(.in = _demux.out, .reset_B = reset_B, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.in,
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.out = synapses,
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.hs_en = register.data[0].d[0].f, // Defaults to handshake disable
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.supply = supply, .reset_B = reset_B);
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(i:N_SYN_DLY_CFG: decoder.dly_cfg[i] = register.data[0].d[1 + i].t); // Defaults to max delay
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// Neurons + encoder
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nrn_hs_2D_array<N_NRN_X,N_NRN_Y,N_LINE_PD_DLY> nrn_grid(.in = neurons,
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.supply = supply, .reset_B = reset_B);
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encoder2D<NC_NRN_X, NC_NRN_Y, N_NRN_X, N_NRN_Y, 16> encoder(
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.inx = nrn_grid.outx,
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.iny = nrn_grid.outy,
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.reset_B = reset_B, .supply = supply
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)
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fifo<NC_NRN_X + NC_NRN_Y, N_BUFFERS> fifo_enc2mrg(.in = encoder.out,
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.reset_B = reset_B, .supply = supply);
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}
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}
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}
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