174 lines
6.2 KiB
Plaintext
174 lines
6.2 KiB
Plaintext
/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/cell_lib_async.act";
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import "../../dataflow_neuro/cell_lib_std.act";
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import "../../dataflow_neuro/treegates.act";
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import "../../dataflow_neuro/primitives.act";
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import std::channel;
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open std::channel;
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// import std::func;
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open std;
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import std::data;
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open std::data;
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namespace tmpl {
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namespace dataflow_neuro {
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/**
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* Bundled data (non dual rail, with req)
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* 2
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* quasi delay insensitive channel (dual rail).
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* Basically a buffer with a bitwise conversion in front of it.
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*/
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export template<pint N, N_dly_cfg, N_dly_cfg2>
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defproc bd2qdi(bd<N> in; avMx1of2<N> out; bool? dly_cfg[N_dly_cfg], dly_cfg2[N_dly_cfg2];
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power supply; bool? reset_B) {
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// Delay on req_in
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bool _req;
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delayprog<N_dly_cfg> dly(.in = in.r, .out = _req, .s = dly_cfg, .supply = supply);
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// sig buff the reset signal
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bool _reset_BX, _reset_BXX[N*2];
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BUF_X4 reset_buf(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<N*2> reset_bufarray(.in=_reset_BX, .out=_reset_BXX, .supply=supply);
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// sig buff the req
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bool _reqX, _reqXX[N*2];
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BUF_X4 req_buf(.a=_req, .y=_reqX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<N*2> req_bufarray(.in=_reqX, .out=_reqXX, .supply=supply);
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// For reasons of pure spice, the control circuitry
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// requires a req signal that FALLS SLOWER than the req going to the function block.
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// Thus need another delay prog.
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bool _req_slowfall;
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delayprog<N_dly_cfg2> dly2(.in = _reqX, .s = dly_cfg2, .supply = supply);
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OR2_X1 req_dly_or(.a = _reqX, .b = dly2.out, .y = _req_slowfall,
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.vss = supply.vss, .vdd = supply.vdd);
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// bd2qdi conversion
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// Each line goes to a t pin, its not to an f.
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bool _inB[N];
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INV_X1 input_invs[N];
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(i:N:
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input_invs[i].a = in.d[i];
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input_invs[i].y = _inB[i];
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input_invs[i].vss = supply.vss;
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input_invs[i].vdd = supply.vdd;
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)
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// BUFFER
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// Basically the buffer_s but with the validity tree ripped out
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// and just connected to in_req instead.
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// And probably need a delay on the in_ack to ensure en has time to disable
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// before the inputs go to another state.
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// Actually apparently no: there is a fixed, huge delay, already incurred
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// by communicating with pads-> uC -> windows 95 and back again.
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// Since the input is never invalid, also need a mechanism
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// for the output to become invalid, when an out_ack is received.
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//control
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bool _en;
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A_3C_RB_X4 inack_ctl(.c1=_en,.c2=_req_slowfall,.c3=out.v,.y=in.a,.pr_B=_reset_BX,.sr_B=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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A_1C1P_X1 en_ctl(.c1=in.a,.p1=out.v,.y=_en,.vdd=supply.vdd,.vss=supply.vss);
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//function
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bool _out_a_B;
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A_2C2N_RB_X4 f_buf_func[N];
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A_2C2N_RB_X4 t_buf_func[N];
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sigbuf<N*2> en_buf(.in=_en, .supply=supply);
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INV_X1 out_a_inv(.a=out.a,.y=_out_a_B, .vss = supply.vss, .vdd = supply.vdd);
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sigbuf<N*2> out_a_B_buf(.in=_out_a_B, .supply=supply);
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// check if you can also do single var to array connect a=b[N]
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// and remove them from the loop
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(i:N:
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f_buf_func[i].y=out.d.d[i].f;
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t_buf_func[i].y=out.d.d[i].t;
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f_buf_func[i].c1=en_buf.out[i];
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t_buf_func[i].c1=en_buf.out[i+N];
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f_buf_func[i].c2=out_a_B_buf.out[i];
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t_buf_func[i].c2=out_a_B_buf.out[i+N];
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f_buf_func[i].n1=_inB[i];
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t_buf_func[i].n1=in.d[i];
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f_buf_func[i].n2=_reqXX[i];
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t_buf_func[i].n2=_reqXX[i+N];
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f_buf_func[i].vdd=supply.vdd;
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t_buf_func[i].vdd=supply.vdd;
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f_buf_func[i].vss=supply.vss;
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t_buf_func[i].vss=supply.vss;
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t_buf_func[i].pr_B = _reset_BXX[i];
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t_buf_func[i].sr_B = _reset_BXX[i];
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f_buf_func[i].pr_B = _reset_BXX[i+N];
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f_buf_func[i].sr_B = _reset_BXX[i+N];
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)
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}
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/**
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* quasi delay insensitive channel (dual rail).
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* 2
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* Bundled data (non dual rail, with req)
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*/
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export template<pint N, N_dly_cfg>
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defproc qdi2bd(avMx1of2<N> in; bd<N> out; bool? dly_cfg[N_dly_cfg]; power supply; bool? reset_B) {
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// Buffer
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buffer<N> buf(.in = in, .supply = supply, .reset_B = reset_B);
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buf.out.a = out.a;
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// Vtree
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vtree<N> out_vtree(.supply = supply);
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(i:N:
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out_vtree.in.d[i].t = buf.out.d.d[i].t;
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out_vtree.in.d[i].f = buf.out.d.d[i].f;
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)
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buf.out.v = out_vtree.out;
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// Delay
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delayprog<N_dly_cfg> dly(.in = out_vtree.out, .out = out.r, .s = dly_cfg, .supply = supply);
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out_vtree.out = dly.in;
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// Wire output data bits to buffer True lines
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(i:N:
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buf.out.d.d[i].t = out.d[i];
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)
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}
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}
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} |