actlib_dataflow_neuro/test/unit_tests/nrn_hs_2d.v

//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
   output y;
   input a;

// -- signals ---
   reg y;
   wire a;

// --- instances
endmodule

//
// Verilog module for: A_2P_U_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4(p1, p2, y);
   input p1;
   input p2;
   output y;

// -- signals ---
   reg y;
   wire p2;
   wire p1;

// --- instances
endmodule

//
// Verilog module for: INV_X2<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X2(y, a);
   output y;
   input a;

// -- signals ---
   reg y;
   wire a;

// --- instances
endmodule

//
// Verilog module for: A_2C1N_RB_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1(y, c1, c2, n1, pr_B, sr_B);
   output y;
   input c1;
   input c2;
   input n1;
   input pr_B;
   input sr_B;

// -- signals ---
   wire sr_B;
   reg y;
   wire c2;
   wire c1;
   reg _y;
   wire pr_B;
   wire n1;

// --- instances
endmodule

//
// Verilog module for: BUF_X2<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X2(y, a);
   output y;
   input a;

// -- signals ---
   reg y;
   reg _y;
   wire a;

// --- instances
endmodule

//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
   output y;
   input c1;
   input p1;

// -- signals ---
   wire c1;
   wire p1;
   reg y;

// --- instances
endmodule

//
// Verilog module for: A_2C1P1N_RB_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1(y, c1, c2, p1, n1, pr_B, sr_B);
   output y;
   input c1;
   input c2;
   input p1;
   input n1;
   input pr_B;
   input sr_B;

// -- signals ---
   wire sr_B;
   wire n1;
   wire p1;
   wire c2;
   reg y;
   wire c1;
   reg _y;
   wire pr_B;

// --- instances
endmodule

//
// Verilog module for: A_3P_U_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4(p1, p2, p3, y);
   input p1;
   input p2;
   input p3;
   output y;

// -- signals ---
   wire p2;
   wire p3;
   wire p1;
   reg y;

// --- instances
endmodule

//
// Verilog module for: nrn_hs_2d<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a , reset_B);
   input \in.d.d[0] ;
   output \in.a ;
   output \outx.d.d[0] ;
   input \outx.a ;
   output \outy.d.d[0] ;
   input \outy.a ;
   input reset_B;

// -- signals ---
   reg \outx.d.d[0] ;
   reg \in.a ;
   reg _reqB;
   reg \outy.d.d[0] ;
   wire reset_B;
   reg _y_a_B;
   wire \outy.a ;
   reg _x_a_B;
   reg _reset_BX;
   wire \in.d.d[0] ;
   wire \outx.a ;
   reg _en;
   reg _req;

// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \req_inv  (.y(_reqB), .a(_req));
_0_0tmpl_0_0dataflow__neuro_0_0A__2P__U__X4 \pu_y  (.p1(_reqB), .p2(\outy.a ), .y(\outy.d.d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_x  (.y(_x_a_B), .a(\outx.a ));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X2 \inv_y  (.y(_y_a_B), .a(\outy.a ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X1 \A_ack  (.y(\in.a ), .c1(_en), .c2(\in.d.d[0] ), .n1(_req), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X2 \reset_buf  (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \A_en  (.y(_en), .c1(\in.a ), .p1(_req));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1P1N__RB__X1 \A_req  (.y(_req), .c1(_en), .c2(_y_a_B), .p1(_x_a_B), .n1(\in.d.d[0] ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0A__3P__U__X4 \pu_x  (.p1(\outx.a ), .p2(_reqB), .p3(_y_a_B), .y(\outx.d.d[0] ));
endmodule

//
// Verilog module for: nrn_hs_2d_inst<>
//
module nrn__hs__2d__inst(\in.d.d[0] , \in.a , \outx.d.d[0] , \outx.a , \outy.d.d[0] , \outy.a );
   input \in.d.d[0] ;
   output \in.a ;
   output \outx.d.d[0] ;
   input \outx.a ;
   output \outy.d.d[0] ;
   input \outy.a ;

// -- signals ---
   reg \outx.d.d[0] ;
   wire \outy.a ;
   wire \in.d.d[0] ;
   reg \outy.d.d[0] ;
   reg _reset_B;
   wire \outx.a ;
   reg \in.a ;

// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0nrn__hs__2d \b  (.\in.d.d[0] (\in.d.d[0] ), .\in.a (\in.a ), .\outx.d.d[0] (\outx.d.d[0] ), .\outx.a (\outx.a ), .\outy.d.d[0] (\outy.d.d[0] ), .\outy.a (\outy.a ), .reset_B(_reset_B));
endmodule