328 lines
11 KiB
Verilog
328 lines
11 KiB
Verilog
module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_364_746_4(Iin0 , Iin1 , Iin2 , Iin3 , Iin4 , Iin5 , Iin6 , Iin7 , Iin8 , Iin9 , Iin10 , Iin11 , Iin12 , Iin13 , Iin14 , Iin15 , Iin16 , Iin17 , Iin18 , Iin19 , Iin20 , Iin21 , Iin22 , Iin23 , Iin24 , Iin25 , Iin26 , Iin27 , Iin28 , Iin29 , Iin30 , Iin31 , Iin32 , Iin33 , Iin34 , Iin35 , Iin36 , Iin37 , Iin38 , Iin39 , Iin40 , Iin41 , Iin42 , Iin43 , Iin44 , Iin45 , Iin46 , Iin47 , Iin48 , Iin49 , Iin50 , Iin51 , Iin52 , Iin53 , Iin54 , Iin55 , Iin56 , Iin57 , Iin58 , Iin59 , Iin60 , Iin61 , Iin62 , Iin63 , Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , Iout30 , Iout31 , Iout32 , Iout33 , Iout34 , Iout35 , Iout36 , Iout37 , Iout38 , Iout39 , Iout40 , Iout41 , Iout42 , Iout43 , Iout44 , Iout45 , Iout46 , Iout47 , Iout48 , Iout49 , Iout50 , Iout51 , Iout52 , Iout53 , Iout54 , Iout55 , Iout56 , Iout57 , Iout58 , Iout59 , Iout60 , Iout61 , Iout62 , Iout63 , vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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input Iin3 ;
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input Iin4 ;
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input Iin5 ;
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input Iin6 ;
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input Iin7 ;
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input Iin8 ;
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input Iin9 ;
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input Iin10 ;
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input Iin11 ;
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input Iin12 ;
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input Iin13 ;
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input Iin14 ;
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input Iin15 ;
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input Iin16 ;
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input Iin17 ;
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input Iin18 ;
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input Iin19 ;
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input Iin20 ;
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input Iin21 ;
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input Iin22 ;
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input Iin23 ;
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input Iin24 ;
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input Iin25 ;
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input Iin26 ;
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input Iin27 ;
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input Iin28 ;
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input Iin29 ;
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input Iin30 ;
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input Iin31 ;
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input Iin32 ;
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input Iin33 ;
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input Iin34 ;
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input Iin35 ;
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input Iin36 ;
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input Iin37 ;
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input Iin38 ;
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input Iin39 ;
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input Iin40 ;
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input Iin41 ;
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input Iin42 ;
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input Iin43 ;
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input Iin44 ;
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input Iin45 ;
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input Iin46 ;
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input Iin47 ;
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input Iin48 ;
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input Iin49 ;
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input Iin50 ;
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input Iin51 ;
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input Iin52 ;
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input Iin53 ;
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input Iin54 ;
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input Iin55 ;
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input Iin56 ;
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input Iin57 ;
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input Iin58 ;
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input Iin59 ;
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input Iin60 ;
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input Iin61 ;
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input Iin62 ;
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input Iin63 ;
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// -- signals ---
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output Iout62 ;
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wire Iin56 ;
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wire Iin52 ;
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output Iout30 ;
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output Iout18 ;
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output Iout10 ;
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wire Iin46 ;
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wire Iin30 ;
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wire Iin15 ;
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output Iout54 ;
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output Iout50 ;
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output Iout34 ;
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wire Iin21 ;
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wire Iin17 ;
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output Iout1 ;
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output Iout58 ;
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wire Iin57 ;
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wire Iin9 ;
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output Iout4 ;
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wire Iin45 ;
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wire Iin37 ;
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wire Iin6 ;
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output Iout57 ;
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wire Iin48 ;
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output Iout45 ;
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wire Iin26 ;
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wire Iin1 ;
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wire Iin62 ;
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output Iout40 ;
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output Iout35 ;
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output Iout51 ;
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output Iout20 ;
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wire Iin44 ;
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wire Iin43 ;
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output Iout22 ;
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output Iout60 ;
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wire Iin24 ;
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wire Iin22 ;
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wire Iin18 ;
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wire Iin12 ;
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output Iout5 ;
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output Iout46 ;
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wire Iin42 ;
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output Iout11 ;
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output Iout53 ;
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output Iout49 ;
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output Iout48 ;
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wire Iin36 ;
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wire Iin28 ;
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wire Iin25 ;
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output Iout59 ;
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output Iout52 ;
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output Iout32 ;
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wire Iin31 ;
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output Iout21 ;
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output Iout47 ;
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output Iout41 ;
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output Iout33 ;
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output Iout28 ;
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wire Iin23 ;
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wire Iin0 ;
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wire Iin49 ;
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output Iout27 ;
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wire Iin19 ;
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output Iout8 ;
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output Iout0 ;
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wire Iin39 ;
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wire Iin20 ;
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wire Iin10 ;
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wire Iin3 ;
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wire Iin29 ;
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output Iout17 ;
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wire Iin7 ;
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wire Iin5 ;
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wire Iin60 ;
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output Iout37 ;
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wire Iin35 ;
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output Iout25 ;
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wire Iin40 ;
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output Iout38 ;
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output Iout36 ;
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output Iout29 ;
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output Iout12 ;
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wire Iin11 ;
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wire Iin2 ;
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wire Iin63 ;
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output Iout43 ;
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output Iout26 ;
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output Iout14 ;
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wire Iin13 ;
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wire Iin33 ;
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output Iout23 ;
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wire Iin34 ;
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wire Iin16 ;
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output Iout7 ;
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output Iout56 ;
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wire Iin47 ;
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output Iout9 ;
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wire Iin53 ;
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wire Iin51 ;
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output Iout24 ;
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output Iout3 ;
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output Iout2 ;
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output Iout63 ;
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output Iout61 ;
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output Iout55 ;
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output Iout31 ;
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output Iout6 ;
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wire Iin54 ;
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wire Iin50 ;
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output Iout42 ;
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wire Iin41 ;
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output Iout39 ;
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wire Iin38 ;
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wire Iin32 ;
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wire Iin27 ;
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output Iout16 ;
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output Iout15 ;
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output Iout13 ;
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wire Iin8 ;
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wire Iin61 ;
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output Iout19 ;
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wire Iin14 ;
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wire Iin4 ;
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wire Iin59 ;
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wire Iin58 ;
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output Iout44 ;
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wire Iin55 ;
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// --- instances
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb0 (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb1 (.in(Iin1 ), .Iout0 (Iout1 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb2 (.in(Iin2 ), .Iout0 (Iout2 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb3 (.in(Iin3 ), .Iout0 (Iout3 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb4 (.in(Iin4 ), .Iout0 (Iout4 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb5 (.in(Iin5 ), .Iout0 (Iout5 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb6 (.in(Iin6 ), .Iout0 (Iout6 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb7 (.in(Iin7 ), .Iout0 (Iout7 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb8 (.in(Iin8 ), .Iout0 (Iout8 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb9 (.in(Iin9 ), .Iout0 (Iout9 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb10 (.in(Iin10 ), .Iout0 (Iout10 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb11 (.in(Iin11 ), .Iout0 (Iout11 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb12 (.in(Iin12 ), .Iout0 (Iout12 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb13 (.in(Iin13 ), .Iout0 (Iout13 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb14 (.in(Iin14 ), .Iout0 (Iout14 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb15 (.in(Iin15 ), .Iout0 (Iout15 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb16 (.in(Iin16 ), .Iout0 (Iout16 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb17 (.in(Iin17 ), .Iout0 (Iout17 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb18 (.in(Iin18 ), .Iout0 (Iout18 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb19 (.in(Iin19 ), .Iout0 (Iout19 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb20 (.in(Iin20 ), .Iout0 (Iout20 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb21 (.in(Iin21 ), .Iout0 (Iout21 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb22 (.in(Iin22 ), .Iout0 (Iout22 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb23 (.in(Iin23 ), .Iout0 (Iout23 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb24 (.in(Iin24 ), .Iout0 (Iout24 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb25 (.in(Iin25 ), .Iout0 (Iout25 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb26 (.in(Iin26 ), .Iout0 (Iout26 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb27 (.in(Iin27 ), .Iout0 (Iout27 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb28 (.in(Iin28 ), .Iout0 (Iout28 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb29 (.in(Iin29 ), .Iout0 (Iout29 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb30 (.in(Iin30 ), .Iout0 (Iout30 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb31 (.in(Iin31 ), .Iout0 (Iout31 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb32 (.in(Iin32 ), .Iout0 (Iout32 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb33 (.in(Iin33 ), .Iout0 (Iout33 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb34 (.in(Iin34 ), .Iout0 (Iout34 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb35 (.in(Iin35 ), .Iout0 (Iout35 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb36 (.in(Iin36 ), .Iout0 (Iout36 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb37 (.in(Iin37 ), .Iout0 (Iout37 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb38 (.in(Iin38 ), .Iout0 (Iout38 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb39 (.in(Iin39 ), .Iout0 (Iout39 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb40 (.in(Iin40 ), .Iout0 (Iout40 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb41 (.in(Iin41 ), .Iout0 (Iout41 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb42 (.in(Iin42 ), .Iout0 (Iout42 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb43 (.in(Iin43 ), .Iout0 (Iout43 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb44 (.in(Iin44 ), .Iout0 (Iout44 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb45 (.in(Iin45 ), .Iout0 (Iout45 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb46 (.in(Iin46 ), .Iout0 (Iout46 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb47 (.in(Iin47 ), .Iout0 (Iout47 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb48 (.in(Iin48 ), .Iout0 (Iout48 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb49 (.in(Iin49 ), .Iout0 (Iout49 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb50 (.in(Iin50 ), .Iout0 (Iout50 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb51 (.in(Iin51 ), .Iout0 (Iout51 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb52 (.in(Iin52 ), .Iout0 (Iout52 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb53 (.in(Iin53 ), .Iout0 (Iout53 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb54 (.in(Iin54 ), .Iout0 (Iout54 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb55 (.in(Iin55 ), .Iout0 (Iout55 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb56 (.in(Iin56 ), .Iout0 (Iout56 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb57 (.in(Iin57 ), .Iout0 (Iout57 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb58 (.in(Iin58 ), .Iout0 (Iout58 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb59 (.in(Iin59 ), .Iout0 (Iout59 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb60 (.in(Iin60 ), .Iout0 (Iout60 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb61 (.in(Iin61 ), .Iout0 (Iout61 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb62 (.in(Iin62 ), .Iout0 (Iout62 ), .vdd(vdd), .vss(vss));
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tmpl_0_0dataflow__neuro_0_0sigbuf_346_4 Isb63 (.in(Iin63 ), .Iout0 (Iout63 ), .vdd(vdd), .vss(vss));
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endmodule |