187 lines
3.1 KiB
Plaintext
187 lines
3.1 KiB
Plaintext
watchall
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set c.bd_dly_cfg[0] 1
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set c.bd_dly_cfg[1] 1
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set c.bd_dly_cfg[2] 1
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set c.bd_dly_cfg[3] 1
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set c.bd_dly_cfg2[0] 1
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set c.bd_dly_cfg2[1] 1
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set c.synapses[0].a 0
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set c.synapses[1].a 0
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set c.synapses[2].a 0
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set c.synapses[3].a 0
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set c.synapses[4].a 0
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set c.synapses[5].a 0
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set c.neurons[0].r 0
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set c.neurons[1].r 0
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set c.neurons[2].r 0
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set c.neurons[3].r 0
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set c.neurons[4].r 0
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set c.neurons[5].r 0
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set-bd-channel-neutral "c.in" 30
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set c.out.a 0
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set c.loopback_en 1
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set Reset 1
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cycle
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mode run
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status X
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system "echo '[] Set reset 0'"
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status X
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set Reset 0
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cycle
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# Reading address 0
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set-bd-data-valid "c.in" 30 536870912
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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# Should first get loopback
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assert-bd-channel-valid "c.out" 30 536870912
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 30
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set c.out.a 0
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cycle
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# Expect register read packet to arrive
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# Receiving output 0 from register 0
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assert-bd-channel-valid "c.out" 30 0
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 30
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set c.out.a 0
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cycle
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# Disable loopback cus it's annoying
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set c.loopback_en 0
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cycle
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# Enables hs, disable synapse delays
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# Writing 255 to address 0
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set-bd-data-valid "c.in" 30 805322688
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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# Remove input
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set-bd-channel-neutral "c.in" 30
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cycle
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assert c.in.a 0
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# Sending spike to synapse [1,2]
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set-bd-data-valid "c.in" 30 5
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cycle
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set c.in.r 1
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cycle
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assert c.in.a 1
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assert c.synapses[5].r 1
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set c.neurons[5].r 1
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cycle
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assert c.neurons[5].a 1
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set c.synapses[5].a 1
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cycle
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assert c.synapses[5].r 0
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set c.neurons[5].r 0
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cycle
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assert c.neurons[5].a 0
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# Receiving output spike [1,2]
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assert-bd-channel-valid "c.out" 30 5
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set c.out.a 1
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cycle
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assert-bd-channel-neutral "c.out" 30
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set c.out.a 0
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cycle
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# # Remove input
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# set-bd-channel-neutral "c.in" 30
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# cycle
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# assert c.in.a 0
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# # Writing 3 to address 1 (enable targeting)
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# set-bd-data-valid "c.in" 30 805306561
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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# # Remove input
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# set-bd-channel-neutral "c.in" 30
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# cycle
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# assert c.in.a 0
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# # Writing 511 to address 2 (change nrn targ)
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# set-bd-data-valid "c.in" 30 805339074
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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# assert c.nrn_mon_x[0] 0
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# assert c.nrn_mon_x[1] 0
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# assert c.nrn_mon_x[2] 0
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# assert c.nrn_mon_x[3] 1
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# assert c.nrn_mon_y[0] 0
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# assert c.nrn_mon_y[1] 0
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# assert c.nrn_mon_y[2] 0
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# assert c.nrn_mon_y[3] 0
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# assert c.nrn_mon_y[4] 0
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# assert c.nrn_mon_y[5] 0
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# assert c.nrn_mon_y[6] 0
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# assert c.nrn_mon_y[7] 1
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# # Remove input
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# set-bd-channel-neutral "c.in" 30
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# cycle
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# assert c.in.a 0
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# # Writing 0 to address 1 (disable targetting)
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# set-bd-data-valid "c.in" 30 805306369
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# cycle
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# set c.in.r 1
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# cycle
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# assert c.in.a 1
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# assert c.nrn_mon_x[0] 0
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# assert c.nrn_mon_x[1] 0
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# assert c.nrn_mon_x[2] 0
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# assert c.nrn_mon_x[3] 0
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# assert c.nrn_mon_y[0] 0
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# assert c.nrn_mon_y[1] 0
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# assert c.nrn_mon_y[2] 0
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# assert c.nrn_mon_y[3] 0
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# assert c.nrn_mon_y[4] 0
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# assert c.nrn_mon_y[5] 0
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# assert c.nrn_mon_y[6] 0
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# assert c.nrn_mon_y[7] 0
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# # Remove input
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# set-bd-channel-neutral "c.in" 30
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# cycle
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# assert c.in.a 0
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