Initial commit

sim/top_interface_tb.sv

@@ -0,0 +1,70 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/16/2026 07:33:07 PM
+// Design Name: 
+// Module Name: top_interface_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define CLK_HALF_PERIOD             2
+
+module top_interface_tb(
+
+    );
+    logic CLK;
+    logic RSTN;
+    logic AERIN_REQ;
+    logic AERIN_ACK;
+    logic [4:0] AERIN_ADDR;
+    
+    logic AEROUT_ACK;
+    logic [8:0] AEROUT_ADDR_T;
+    logic [8:0] AEROUT_ADDR_F;
+    
+    initial begin
+        CLK = 1'b0;
+        forever #(`CLK_HALF_PERIOD) CLK = ~CLK;
+    end
+    
+    assign RST = !RSTN;
+    
+    top_interface #() ut (
+        .CLK(CLK),
+        .RSTN_O(RSTN),
+        .AERIN_REQ(AERIN_REQ),
+        .AERIN_ADDR(AERIN_ADDR),
+        .AERIN_ACK(AERIN_ACK),
+        .AEROUT_ACK(AEROUT_ACK),
+        .AEROUT_ADDR_T(AEROUT_ADDR_T),
+        .AEROUT_ADDR_F(AEROUT_ADDR_F)
+    );
+    
+    autoack auto_ack (
+        .CLK(CLK),  
+        .RST(RST),  
+        .OUTPUT_BITS_ONION_p(AEROUT_ADDR_T),
+        .OUTPUT_BITS_ONION_n(AEROUT_ADDR_F),
+        .OUTPUT_BITS_ONION_A_AO(AEROUT_ACK)
+    );
+    
+    stimulus_gen #() stim (
+        .CLK_I(CLK),
+        .RST_I(RST),
+        .REQ_O(AERIN_REQ),
+        .ACK_I(AERIN_ACK),
+        .ADDR_O(AERIN_ADDR)
+    );
+endmodule