actlib_dataflow_neuro/test/unit_tests/texel_in30_noNrn/test.prsim

watchall


set c.bd_dly_cfg[0] 1
set c.bd_dly_cfg[1] 1
set c.bd_dly_cfg[2] 1
set c.bd_dly_cfg[3] 1

set c.bd_dly_cfg2[0] 1
set c.bd_dly_cfg2[1] 1

set c.synapses[0].a 0
set c.synapses[1].a 0
set c.synapses[2].a 0
set c.synapses[3].a 0
set c.synapses[4].a 0
set c.synapses[5].a 0

set c.neurons[0].r 0
set c.neurons[1].r 0
set c.neurons[2].r 0
set c.neurons[3].r 0
set c.neurons[4].r 0
set c.neurons[5].r 0



set-bd-channel-neutral "c.in" 30
set c.out.a 0
set c.loopback_en 1
set Reset 1

cycle

mode run
status X
system "echo '[] Set reset 0'"
status X
set Reset 0
cycle

# Reading address 0
set-bd-data-valid "c.in" 30 536870912
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 30
cycle
assert c.in.a 0

# Should first get loopback
assert-bd-channel-valid "c.out" 30 536870912
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 30
set c.out.a 0
cycle

# Expect register read packet to arrive
# Receiving output 0 from register 0
assert-bd-channel-valid "c.out" 30 0
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 30
set c.out.a 0
cycle

# Disable loopback cus it's annoying
set c.loopback_en 0
cycle

# Enables hs, disable synapse delays
# Writing 255 to address 0
set-bd-data-valid "c.in" 30 805322688
cycle
set c.in.r 1
cycle
assert c.in.a 1


# Remove input
set-bd-channel-neutral "c.in" 30
cycle
assert c.in.a 0

# Sending spike to synapse [1,2]
set-bd-data-valid "c.in" 30 5
cycle
set c.in.r 1
cycle
assert c.in.a 1

assert c.synapses[5].r 1
set c.neurons[5].r 1
cycle
assert c.neurons[5].a 1
set c.synapses[5].a 1
cycle
assert c.synapses[5].r 0
set c.neurons[5].r 0
cycle
assert c.neurons[5].a 0


# Receiving output spike [1,2]
assert-bd-channel-valid "c.out" 30 5
set c.out.a 1
cycle
assert-bd-channel-neutral "c.out" 30
set c.out.a 0
cycle


# # Remove input
# set-bd-channel-neutral "c.in" 30
# cycle
# assert c.in.a 0


# # Writing 3 to address 1 (enable targeting)
# set-bd-data-valid "c.in" 30 805306561
# cycle
# set c.in.r 1
# cycle
# assert c.in.a 1

# # Remove input
# set-bd-channel-neutral "c.in" 30
# cycle
# assert c.in.a 0

# # Writing 511 to address 2 (change nrn targ)
# set-bd-data-valid "c.in" 30 805339074
# cycle
# set c.in.r 1
# cycle
# assert c.in.a 1

# assert c.nrn_mon_x[0] 0
# assert c.nrn_mon_x[1] 0
# assert c.nrn_mon_x[2] 0
# assert c.nrn_mon_x[3] 1

# assert c.nrn_mon_y[0] 0
# assert c.nrn_mon_y[1] 0
# assert c.nrn_mon_y[2] 0
# assert c.nrn_mon_y[3] 0
# assert c.nrn_mon_y[4] 0
# assert c.nrn_mon_y[5] 0
# assert c.nrn_mon_y[6] 0
# assert c.nrn_mon_y[7] 1

# # Remove input
# set-bd-channel-neutral "c.in" 30
# cycle
# assert c.in.a 0

# # Writing 0 to address 1 (disable targetting)
# set-bd-data-valid "c.in" 30 805306369
# cycle
# set c.in.r 1
# cycle
# assert c.in.a 1

# assert c.nrn_mon_x[0] 0
# assert c.nrn_mon_x[1] 0
# assert c.nrn_mon_x[2] 0
# assert c.nrn_mon_x[3] 0

# assert c.nrn_mon_y[0] 0
# assert c.nrn_mon_y[1] 0
# assert c.nrn_mon_y[2] 0
# assert c.nrn_mon_y[3] 0
# assert c.nrn_mon_y[4] 0
# assert c.nrn_mon_y[5] 0
# assert c.nrn_mon_y[6] 0
# assert c.nrn_mon_y[7] 0

# # Remove input
# set-bd-channel-neutral "c.in" 30
# cycle
# assert c.in.a 0