texel30 with manual neurons passing tests

test/unit_tests/texel_in30_noNrn/test.act

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+/*************************************************************************
+ *
+ *  This file is part of ACT dataflow neuro library.
+ * It's the testing facility for cell_lib_std.act
+ *
+ *  Copyright (c) 2022 University of Groningen - Ole Richter  
+ *  Copyright (c) 2022 University of Groningen - Hugh Greatorex
+ *  Copyright (c) 2022 University of Groningen - Michele Mastella
+ *  Copyright (c) 2022 University of Groningen - Madison Cotteret
+ *
+ *  This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
+ *
+ *  You may redistribute and modify this documentation and make products
+ *  using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
+ *  This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
+ *  AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
+ *  for applicable conditions.
+ *
+ *  Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
+ *
+ *  As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
+ *  these sources, You must maintain the Source Location visible in its
+ *  documentation.
+ *
+ **************************************************************************
+ */
+
+import "../../dataflow_neuro/coders.act";
+import "../../dataflow_neuro/primitives.act";
+import "../../dataflow_neuro/chips.act";
+
+import globals;
+import std::data;
+
+open std::data;
+
+
+open tmpl::dataflow_neuro;
+
+defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
+    a1of1 synapses[6];
+    a1of1 neurons[6];
+    bool? nrn_mon_x[4], nrn_mon_y[8], syn_mon_x[4], syn_mon_y[8];
+    bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
+
+    bool _reset_B; 
+    prs {
+        Reset => _reset_B-
+    }
+    power supply;
+    supply.vdd = Vdd;
+    supply.vss = GND;
+
+    pint N_IN = 30;
+    
+    pint N_NRN_X = 2;
+    pint N_NRN_Y = 3;
+    // pint NC_NRN_X = std:ceil_log2(N_NRN_X);
+    // pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
+    pint NC_NRN_X = 1;
+    pint NC_NRN_Y = 2;
+
+    pint N_SYN_X = 2;
+    pint N_SYN_Y = 3;
+    // pint NC_SYN_X = std:ceil_log2(N_SYN_X);
+    // pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
+    pint NC_SYN_X = 1;
+    pint NC_SYN_Y = 2;
+
+    pint N_SYN_DLY_CFG = 4;
+    pint N_BD_DLY_CFG = 4;
+    pint N_BD_DLY_CFG2 = 2;
+
+    pint N_NRN_MON_X = 4;
+    pint N_NRN_MON_Y = 8;
+    pint N_SYN_MON_X = 4;
+    pint N_SYN_MON_Y = 8;
+
+    pint N_BUFFERS = 3;
+
+    pint N_LINE_PD_DLY = 3;
+    
+    pint REG_NCA = 6;
+    pint REG_M = 1<<REG_NCA;
+    pint REG_NCW = 22;
+
+    chip_texel<N_IN,
+    N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
+    NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
+    N_SYN_DLY_CFG,
+    N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
+    N_BUFFERS,
+    N_LINE_PD_DLY,
+    N_BD_DLY_CFG, N_BD_DLY_CFG2,
+    REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
+        .synapses = synapses, .neurons = neurons,
+        .nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
+        .syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
+        .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
+        .reset_B = _reset_B, .supply = supply);
+
+}
+
+
+// fifo_decoder_neurons_encoder_fifo e;
+chip_texel_in30 c; 

test/unit_tests/texel_in30_noNrn/test.prsim

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+watchall
+
+
+set c.bd_dly_cfg[0] 1
+set c.bd_dly_cfg[1] 1
+set c.bd_dly_cfg[2] 1
+set c.bd_dly_cfg[3] 1
+
+set c.bd_dly_cfg2[0] 1
+set c.bd_dly_cfg2[1] 1
+
+set c.synapses[0].a 0
+set c.synapses[1].a 0
+set c.synapses[2].a 0
+set c.synapses[3].a 0
+set c.synapses[4].a 0
+set c.synapses[5].a 0
+
+set c.neurons[0].r 0
+set c.neurons[1].r 0
+set c.neurons[2].r 0
+set c.neurons[3].r 0
+set c.neurons[4].r 0
+set c.neurons[5].r 0
+
+
+
+set-bd-channel-neutral "c.in" 30
+set c.out.a 0
+set c.loopback_en 1
+set Reset 1
+
+cycle
+
+mode run
+status X
+system "echo '[] Set reset 0'"
+status X
+set Reset 0
+cycle
+
+# Reading address 0
+set-bd-data-valid "c.in" 30 536870912
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
+
+# Should first get loopback
+assert-bd-channel-valid "c.out" 30 536870912
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+# Expect register read packet to arrive
+# Receiving output 0 from register 0
+assert-bd-channel-valid "c.out" 30 0
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+# Disable loopback cus it's annoying
+set c.loopback_en 0
+cycle
+
+# Enables hs, disable synapse delays
+# Writing 255 to address 0
+set-bd-data-valid "c.in" 30 805322688
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+
+# Remove input
+set-bd-channel-neutral "c.in" 30
+cycle
+assert c.in.a 0
+
+# Sending spike to synapse [1,2]
+set-bd-data-valid "c.in" 30 5
+cycle
+set c.in.r 1
+cycle
+assert c.in.a 1
+
+assert c.synapses[5].r 1
+set c.neurons[5].r 1
+cycle
+assert c.neurons[5].a 1
+set c.synapses[5].a 1
+cycle
+assert c.synapses[5].r 0
+set c.neurons[5].r 0
+cycle
+assert c.neurons[5].a 0
+
+
+# Receiving output spike [1,2]
+assert-bd-channel-valid "c.out" 30 5
+set c.out.a 1
+cycle
+assert-bd-channel-neutral "c.out" 30
+set c.out.a 0
+cycle
+
+
+# # Remove input
+# set-bd-channel-neutral "c.in" 30
+# cycle
+# assert c.in.a 0
+
+
+# # Writing 3 to address 1 (enable targeting)
+# set-bd-data-valid "c.in" 30 805306561
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1
+
+# # Remove input
+# set-bd-channel-neutral "c.in" 30
+# cycle
+# assert c.in.a 0
+
+# # Writing 511 to address 2 (change nrn targ)
+# set-bd-data-valid "c.in" 30 805339074
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1
+
+# assert c.nrn_mon_x[0] 0
+# assert c.nrn_mon_x[1] 0
+# assert c.nrn_mon_x[2] 0
+# assert c.nrn_mon_x[3] 1
+
+# assert c.nrn_mon_y[0] 0
+# assert c.nrn_mon_y[1] 0
+# assert c.nrn_mon_y[2] 0
+# assert c.nrn_mon_y[3] 0
+# assert c.nrn_mon_y[4] 0
+# assert c.nrn_mon_y[5] 0
+# assert c.nrn_mon_y[6] 0
+# assert c.nrn_mon_y[7] 1
+
+# # Remove input
+# set-bd-channel-neutral "c.in" 30
+# cycle
+# assert c.in.a 0
+
+# # Writing 0 to address 1 (disable targetting)
+# set-bd-data-valid "c.in" 30 805306369
+# cycle
+# set c.in.r 1
+# cycle
+# assert c.in.a 1
+
+# assert c.nrn_mon_x[0] 0
+# assert c.nrn_mon_x[1] 0
+# assert c.nrn_mon_x[2] 0
+# assert c.nrn_mon_x[3] 0
+
+# assert c.nrn_mon_y[0] 0
+# assert c.nrn_mon_y[1] 0
+# assert c.nrn_mon_y[2] 0
+# assert c.nrn_mon_y[3] 0
+# assert c.nrn_mon_y[4] 0
+# assert c.nrn_mon_y[5] 0
+# assert c.nrn_mon_y[6] 0
+# assert c.nrn_mon_y[7] 0
+
+# # Remove input
+# set-bd-channel-neutral "c.in" 30
+# cycle
+# assert c.in.a 0