actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_33_740_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_33_740_4(Iin0 , Iin1 , Iin2 , Iout0 , Iout1 , Iout2 , vdd, vss); 
   input vdd;
   input vss;
   input Iin0 ;
   input Iin1 ;
   input Iin2 ;
   
   
   

// -- signals ---
   output Iout2 ;
   wire Iin1 ;
   wire Iin0 ;
   output Iout1 ;
   wire Iin2 ;
   output Iout0 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0sigbuf_340_4 Isb0  (.in(Iin0 ), .Iout0 (Iout0 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_340_4 Isb1  (.in(Iin1 ), .Iout0 (Iout1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_340_4 Isb2  (.in(Iin2 ), .Iout0 (Iout2 ), .vdd(vdd), .vss(vss));
endmodule