actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0andtree_33_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vss); 
   input vdd;
   input vss;
   input Iin0 ;
   input Iin1 ;
   input Iin2 ;
   output out;

// -- signals ---
   wire Iin1 ;
   wire out ;
   wire Iin0 ;
   wire Iin2 ;

// --- instances
AND3_X1 Iand3s0  (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));
endmodule