17 lines
364 B
Verilog
17 lines
364 B
Verilog
module tmpl_0_0dataflow__neuro_0_0andtree_33_4(Iin0 , Iin1 , Iin2 , out, vdd, vss);
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input vdd;
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input vss;
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input Iin0 ;
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input Iin1 ;
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input Iin2 ;
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output out;
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// -- signals ---
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wire Iin1 ;
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wire out ;
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wire Iin0 ;
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wire Iin2 ;
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// --- instances
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AND3_X1 Iand3s0 (.y(out), .a(Iin0 ), .b(Iin1 ), .c(Iin2 ), .vdd(vdd), .vss(vss));
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endmodule |