actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0append_37_724_70_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0append_37_724_70_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iout_d_d7_d0 , vdd, vss); 
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   

// -- signals ---
   wire Iin_d_d6_d1 ;
   wire Iin_d_d2_d0 ;
   wire Iin_d_d4_d1 ;
   wire Iin_d_d0_d1 ;
   wire Iin_d_d3_d0 ;
   wire Isb_in ;
   wire Iin_d_d5_d1 ;
   wire Iin_d_d3_d1 ;
   wire Iin_d_d1_d0 ;
   wire Iin_d_d0_d0 ;
   wire Iin_d_d6_d0 ;
   output Iout_d_d7_d0 ;
   wire Iin_d_d2_d1 ;
   wire Iin_d_d1_d1 ;
   wire Iin_d_d4_d0 ;
   wire Iin_d_d5_d0 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0vtree_37_4 Iin_val  (.Iin_d0_d0 (Iin_d_d0_d0 ), .Iin_d0_d1 (Iin_d_d0_d1 ), .Iin_d1_d0 (Iin_d_d1_d0 ), .Iin_d1_d1 (Iin_d_d1_d1 ), .Iin_d2_d0 (Iin_d_d2_d0 ), .Iin_d2_d1 (Iin_d_d2_d1 ), .Iin_d3_d0 (Iin_d_d3_d0 ), .Iin_d3_d1 (Iin_d_d3_d1 ), .Iin_d4_d0 (Iin_d_d4_d0 ), .Iin_d4_d1 (Iin_d_d4_d1 ), .Iin_d5_d0 (Iin_d_d5_d0 ), .Iin_d5_d1 (Iin_d_d5_d1 ), .Iin_d6_d0 (Iin_d_d6_d0 ), .Iin_d6_d1 (Iin_d_d6_d1 ), .out(Isb_in ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_324_4 Isb  (.in(Isb_in ), .Iout0 (Iout_d_d7_d0 ), .vdd(vdd), .vss(vss));
endmodule