107 lines
3.2 KiB
Plaintext
107 lines
3.2 KiB
Plaintext
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/coders.act";
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import "../../dataflow_neuro/primitives.act";
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import "../../dataflow_neuro/chips.act";
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import globals;
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import std::data;
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open std::data;
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open tmpl::dataflow_neuro;
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defproc chip_texel_in30 (bd<30> in; bd<30> out; Mx1of2<22> reg_data[64];
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a1of1 synapses[6];
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a1of1 neurons[6];
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bool? nrn_mon_x[4], nrn_mon_y[8], syn_mon_x[4], syn_mon_y[8];
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bool? bd_dly_cfg[4], bd_dly_cfg2[2], loopback_en){
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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power supply;
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supply.vdd = Vdd;
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supply.vss = GND;
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pint N_IN = 30;
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pint N_NRN_X = 2;
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pint N_NRN_Y = 3;
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// pint NC_NRN_X = std:ceil_log2(N_NRN_X);
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// pint NC_NRN_Y = std:ceil_log2(N_NRN_Y);
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pint NC_NRN_X = 1;
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pint NC_NRN_Y = 2;
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pint N_SYN_X = 2;
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pint N_SYN_Y = 3;
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// pint NC_SYN_X = std:ceil_log2(N_SYN_X);
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// pint NC_SYN_Y = std:ceil_log2(N_SYN_Y);
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pint NC_SYN_X = 1;
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pint NC_SYN_Y = 2;
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pint N_SYN_DLY_CFG = 4;
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pint N_BD_DLY_CFG = 4;
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pint N_BD_DLY_CFG2 = 2;
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pint N_NRN_MON_X = 4;
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pint N_NRN_MON_Y = 8;
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pint N_SYN_MON_X = 4;
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pint N_SYN_MON_Y = 8;
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pint N_BUFFERS = 3;
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pint N_LINE_PD_DLY = 3;
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pint REG_NCA = 6;
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pint REG_M = 1<<REG_NCA;
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pint REG_NCW = 22;
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chip_texel<N_IN,
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N_NRN_X, N_NRN_Y, N_SYN_X, N_SYN_Y,
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NC_NRN_X, NC_NRN_Y, NC_SYN_X, NC_SYN_Y,
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N_SYN_DLY_CFG,
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N_NRN_MON_X, N_NRN_MON_Y, N_SYN_MON_X, N_SYN_MON_Y,
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N_BUFFERS,
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N_LINE_PD_DLY,
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N_BD_DLY_CFG, N_BD_DLY_CFG2,
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REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out, .reg_data = reg_data,
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.synapses = synapses, .neurons = neurons,
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.nrn_mon_x = nrn_mon_x, .nrn_mon_y = nrn_mon_y,
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.syn_mon_x = syn_mon_x, .syn_mon_y = syn_mon_y,
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.bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .loopback_en = loopback_en,
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.reset_B = _reset_B, .supply = supply);
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}
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// fifo_decoder_neurons_encoder_fifo e;
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chip_texel_in30 c;
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