2022-03-14 17:15:27 +01:00
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watchall
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2022-03-09 16:44:44 +01:00
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system "echo '[0] start test'"
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2022-03-09 20:02:41 +01:00
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system "echo '----------------------------------------------------------'"
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2022-03-09 16:44:44 +01:00
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set-qdi-channel-neutral "t.in" 5
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2022-03-15 08:16:59 +01:00
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set-qdi-channel-neutral "t.out" 4
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2022-03-09 16:44:44 +01:00
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set t.data[0].d[0] 0
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set t.data[0].d[1] 0
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set t.data[1].d[0] 0
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set t.data[1].d[1] 0
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2022-03-14 17:15:27 +01:00
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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2022-03-09 20:02:41 +01:00
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set t.out.a 0
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2022-03-14 17:15:27 +01:00
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set t.out.v 0
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2022-03-15 08:16:59 +01:00
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cycle
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2022-03-14 17:15:27 +01:00
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#set t.registers._in_write.a 0
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2022-03-09 16:44:44 +01:00
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set Reset 0
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2022-03-15 08:16:59 +01:00
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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2022-03-09 16:44:44 +01:00
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cycle
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2022-03-15 08:16:59 +01:00
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assert-qdi-channel-neutral "t.in" 5
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assert-qdi-channel-neutral "t.out" 4
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# There shouldnt be any status X
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2022-03-09 16:44:44 +01:00
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status X
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2022-03-14 17:15:27 +01:00
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#mode run
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cycle
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assert-qdi-channel-neutral "t.out" 4
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2022-03-09 16:44:44 +01:00
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assert t.data[0].d[0] 0
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assert t.data[0].d[1] 0
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assert t.data[1].d[0] 0
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assert t.data[1].d[1] 0
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cycle
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system "echo '[1] reset completed'"
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2022-03-09 20:02:41 +01:00
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system "echo '----------------------------------------------------------'"
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2022-03-09 16:44:44 +01:00
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# Set delay config lines
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2022-03-14 17:15:27 +01:00
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2022-03-09 16:44:44 +01:00
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cycle
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system "echo '[2] delay line set'"
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2022-03-09 20:02:41 +01:00
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system "echo '----------------------------------------------------------'"
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2022-03-14 17:15:27 +01:00
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2022-03-09 20:02:41 +01:00
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set-qdi-channel-valid "t.in" 5 3
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2022-03-14 17:15:27 +01:00
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# 3 -> 00011 -> writing mode, address 00, word 11
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2022-03-09 16:44:44 +01:00
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cycle
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2022-03-14 17:15:27 +01:00
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assert t.in.a 1
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assert-qdi-channel-neutral "t.out" 4
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2022-03-09 16:44:44 +01:00
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set-qdi-channel-neutral "t.in" 5
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cycle
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2022-03-14 17:15:27 +01:00
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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2022-03-15 08:16:59 +01:00
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assert t.registers.ff[4].q 0
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assert t.registers.ff[5].q 0
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assert t.registers.ff[6].q 0
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assert t.registers.ff[7].q 0
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2022-03-14 17:15:27 +01:00
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2022-03-09 20:02:41 +01:00
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system "echo '[3] first writing done'"
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system "echo '----------------------------------------------------------'"
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2022-03-14 17:15:27 +01:00
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set-qdi-channel-valid "t.in" 5 16
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2022-03-15 08:16:59 +01:00
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# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
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2022-03-14 17:15:27 +01:00
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cycle
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2022-03-15 08:16:59 +01:00
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assert t.registers._clock_temp_inv 1
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2022-03-14 17:15:27 +01:00
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assert-qdi-channel-valid "t.out" 4 3
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set t.out.v 1
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cycle
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set t.out.a 1
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2022-03-15 08:16:59 +01:00
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assert t.registers._clock_temp_inv 1
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2022-03-14 17:15:27 +01:00
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cycle
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assert t.in.a 1
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set-qdi-channel-neutral "t.in" 5
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2022-03-15 08:16:59 +01:00
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assert t.registers._clock_temp_inv 1
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2022-03-14 17:15:27 +01:00
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cycle
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2022-03-15 08:16:59 +01:00
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assert t.registers._clock_temp_inv 1
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2022-03-14 17:15:27 +01:00
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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assert-qdi-channel-neutral "t.out" 4
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system "echo '[4] reading done'"
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system "echo '----------------------------------------------------------'"
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2022-03-09 16:44:44 +01:00
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