Added new version of Register_rw (still not properly working)
This commit is contained in:
parent
cc2234a1b1
commit
edb0443c01
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@ -373,7 +373,7 @@ namespace tmpl {
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}
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sizing { _en{-2}; y{-2,2} }
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}
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export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q; bool? vdd,vss)
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export defproc DFFQ_R_X1 (bool? clk_B, reset_B, d; bool! q,q_B; bool? vdd,vss)
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{
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bool _clk_B, __clk_B, _mqi,_mqib,_sqi,_sqib;
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prs {
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@ -393,6 +393,8 @@ namespace tmpl {
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_sqib => _sqi-
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_sqib => q-
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q => q_B-
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}
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}
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@ -62,9 +62,9 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supp
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// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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sigbuf_1output<4> clk_X(.in = _clock_temp,.out = _clock,.supply = supply);
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// Sending back to the ackowledge
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delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp_inv, .out = _in_a_temp,.s = dly_cfg, .supply = supply);
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sigbuf_1output<4> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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//Reset Buffers
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
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@ -127,61 +127,65 @@ defproc register_w (avMx1of2<1+lognw+wl> in; d1of<wl> data[1<<lognw]; power supp
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// data -> the data saved in the flip flop, sized wl x nw
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export template<pint lognw,wl,N_dly_cfg>
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defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> data[1<<lognw]; power supply; bool? reset_B,reset_mem_B,dly_cfg[N_dly_cfg]){
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock,_clock_temp_inv;
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bool _ff_v;
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pint nw = 1<<lognw;
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bool _in_v_temp,_in_a_temp,_clock_temp,_clock[nw],_clock_temp_inv, _in_a_write, _in_a_read;
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//Validation of the input
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avMx1of2<lognw+wl> _in_temp2,_in_read,_in_write;
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avMx1of2<1>_in_flag;
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// Read or write?
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AND2_X1 ack_and(.a = _in_temp2.a,.b = _ff_v,.y = in.a,.vdd = supply.vdd,.vss = supply.vss);
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in.v = _in_temp2.v;
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_in_flag.d.d[0] = in.d.d[lognw+wl];
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(i:lognw+wl:_in_temp2.d.d[i] = in.d.d[i];)
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demux<lognw+wl> read_write_demux(.in = _in_temp2,.out1 = _in_read, .out2 = _in_write, .cond = _in_flag,.reset_B = reset_B);
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read_write_demux.supply= supply;
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//WRITE PATH
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// Validation
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Mx1of2<lognw+wl> _in_write_temp;
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(i:lognw+wl:_in_write_temp.d[i] = _in_write.d.d[i];)
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vtree<lognw+wl> val_input_write(.in = _in_write_temp,.out = _in_write.v, .supply = supply);
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// Acknowledgment
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delayprog<N_dly_cfg> ack_dly(.in = _clock, .out = _in_write.a,.s = dly_cfg, .supply = supply);
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// Generation of the fake clock pulse (inverted because the ff clocks are low_active)
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delayprog<N_dly_cfg> clk_dly(.in = _in_write.v, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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vtree<1+lognw+wl> val_input(.in = in.d,.out = _in_v_temp, .supply = supply);
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sigbuf_1output<12> val_input_X(.in = _in_v_temp,.out = in.v,.supply = supply);
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// Acknowledgment
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OR2_X1 ack_readwrite(.a = _in_a_write,.b = _in_a_read,.y = _in_a_temp,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<12> ack_input_X(.in = _in_a_temp,.out = in.a,.supply = supply);
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// WRITE
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// Generation of the fake clock pulse if write is HIGH (inverted because the ff clocks are low_active)
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bool _in_v_temp_write;
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AND2_X1 clk_switch(.a = _in_v_temp,.b = in.d.d[lognw+wl].f, .y = _in_v_temp_write,.vdd = supply.vdd,.vss = supply.vss);
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delayprog<N_dly_cfg> clk_dly(.in = _in_v_temp_write, .out = _clock_temp,.s = dly_cfg, .supply = supply);
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INV_X1 inv_clk(.a = _clock_temp,.y = _clock_temp_inv,.vdd = supply.vdd,.vss = supply.vss);
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sigbuf_1output<4> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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//READ PATH
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//Validation
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Mx1of2<lognw+wl> _in_read_temp;
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(i:lognw+wl:_in_read_temp.d[i] = _in_read.d.d[i];)
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vtree<lognw+wl> val_input_read(.in = _in_read_temp,.out = _in_read.v, .supply = supply);
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vtree<wl> ff_validator;
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Mx1of2<wl> _out_temp;
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(i:wl:_out_temp.d[i] = out.d.d[i];)
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ff_validator.in = _out_temp;
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ff_validator.out = _ff_v;
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ff_validator.supply = supply;
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// Acknowledgment
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_in_read.a = _ff_v; //The circuit is ack when flip flop data are valid
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sigbuf<nw> clk_X(.in = _clock_temp_inv,.out = _clock,.supply = supply);
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sigbuf<wl> clock_buffer[nw];
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bool _clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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// Sending back to the ackowledge
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bool _in_a_write_temp;
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delayprog<N_dly_cfg> ack_dly(.in = _clock_temp, .out = _in_a_write_temp,.s = dly_cfg, .supply = supply);
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AND2_X1 ack_write_and(.a = in.d.d[lognw+wl].f,.b = _in_a_write_temp,.y = _in_a_write,.vdd = supply.vdd, .vss = supply.vss);
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// READ
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//Outputing the word to read
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AND2_X1 word_to_read[nw];
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sigbuf<wl*2> word_to_read_X[nw];
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ortree<nw> bitselector_t[wl];
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ortree<nw> bitselector_f[wl];
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AND2_X1 word_selector_t[nw*wl];
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AND2_X1 word_selector_f[nw*wl];
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bool _out_word_to_read[2*nw*wl];
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buffer_s<lognw+wl> output_buf(.out = out,.supply = supply, .reset_B = reset_B);
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AND2_X1 address_propagator_f[lognw],address_propagator_t[lognw];
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// Outputting the address if the read is true
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(i:lognw:
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address_propagator_t[i].a = in.d.d[lognw+wl].t;
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address_propagator_t[i].b = in.d.d[i+wl].t;
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address_propagator_t[i].y = output_buf.in.d.d[i+wl].t;
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address_propagator_t[i].vdd = supply.vdd;
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address_propagator_t[i].vss = supply.vss;
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address_propagator_f[i].a = in.d.d[lognw+wl].t;
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address_propagator_f[i].b = in.d.d[i+wl].f;
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address_propagator_f[i].y = output_buf.in.d.d[i+wl].f;
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address_propagator_f[i].vdd = supply.vdd;
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address_propagator_f[i].vss = supply.vss;
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)
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AND2_X1 ack_read_and(.a = in.d.d[lognw+wl].t,.b = output_buf.in.a,.y = _in_a_read,.vdd = supply.vdd, .vss = supply.vss);
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//Reset Buffers
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl*2];
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bool _reset_BX,_reset_mem_BX,_reset_mem_BXX[nw*wl];
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BUF_X1 reset_buf_BX(.a=reset_B, .y=_reset_BX,.vdd=supply.vdd,.vss=supply.vss);
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BUF_X1 reset_buf_BXX(.a=reset_mem_B, .y=_reset_mem_BX,.vdd=supply.vdd,.vss=supply.vss);
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sigbuf<nw*wl*2> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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// Creating the different flip flop arrays
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bool _out_encoder[nw],_clock_word_temp[nw],_clock_word[nw],_clock_buffer_out[nw*wl];
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sigbuf<nw*wl> reset_bufarray(.in=_reset_mem_BX, .out=_reset_mem_BXX,.supply=supply);
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//Creating the encoder
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andtree<lognw> atree[nw];
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d1of<wl> _data_f;
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AND2_X1 and_encoder[nw];
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AND3_X1 reading_activator_t[nw*wl],reading_activator_f[nw*wl];
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sigbuf<wl*2> clock_buffer[nw];
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DFFQ_R_X1 ff_t[nw*wl],ff_f[nw*wl];
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OR2_X1 ff_val[wl];
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(i:wl..lognw:out.d.d[i] = in.d.d[i];)
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bool __ffout_dualrail[nw*wl];
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// Creating the different flip flop arrays
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bool _out_encoder[nw];
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DFFQ_R_X1 ff[nw*wl];
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// For loop for assigning the different components
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pint bitval;
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(k:nw:atree[k].supply = supply;)
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(word_idx:nw:
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@ -195,50 +199,50 @@ defproc register_rw (avMx1of2<1+lognw+wl> in; avMx1of2<lognw+wl> out; d1of<wl> d
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[]bitval >= 2 -> {false : "fuck"};
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]
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)
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// Encode which work is the right one
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atree[word_idx].out = _out_encoder[word_idx];
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// READ: use the encoder selection to read the value
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// WRITE: Activating the fake clock for the right word
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atree[word_idx].out = _out_encoder[word_idx];
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and_encoder[word_idx].a = _out_encoder[word_idx];
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and_encoder[word_idx].b = _clock;
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and_encoder[word_idx].b = _clock[word_idx];
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and_encoder[word_idx].y = _clock_word_temp[word_idx];
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and_encoder[word_idx].vdd = supply.vdd;
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and_encoder[word_idx].vss = supply.vss;
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clock_buffer[word_idx].in = _clock_word_temp[word_idx];
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clock_buffer[word_idx].supply = supply;
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// Describing all the FF and their connection
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// READ: Selecting the right word to read if read is high
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word_to_read[word_idx].a = in.d.d[lognw+wl].t;
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word_to_read[word_idx].b = _out_encoder[word_idx];
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word_to_read[word_idx].y = word_to_read_X[word_idx].in;
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word_to_read[word_idx].vdd = supply.vdd;
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word_to_read[word_idx].vss = supply.vss;
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word_to_read_X[word_idx].supply = supply;
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(bit_idx:wl:
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ff_t[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff_t[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff_t[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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ff_t[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
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ff_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff_t[bit_idx+word_idx*(wl)].vss = supply.vss;
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ff_f[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx+wl-1];
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ff_f[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].f;
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ff_f[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)+nw-1];
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ff_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff_f[bit_idx+word_idx*(wl)].vss = supply.vss;
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reading_activator_t[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].t;
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reading_activator_t[bit_idx+word_idx*(wl)].b = ff_t[bit_idx+word_idx*(wl)].q;
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reading_activator_t[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
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reading_activator_t[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].t;
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reading_activator_t[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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reading_activator_t[bit_idx+word_idx*(wl)].vss = supply.vss;
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reading_activator_f[bit_idx+word_idx*(wl)].a = _in_flag.d.d[0].f;
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reading_activator_f[bit_idx+word_idx*(wl)].b = ff_f[bit_idx+word_idx*(wl)].q;
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reading_activator_f[bit_idx+word_idx*(wl)].y = out.d.d[bit_idx].f;
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reading_activator_f[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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reading_activator_f[bit_idx+word_idx*(wl)].vss = supply.vss;
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reading_activator_f[bit_idx+word_idx*(wl)].c = _out_encoder[word_idx];
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// Describing all the FF and their connection
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ff[bit_idx+word_idx*(wl)].clk_B = clock_buffer[word_idx].out[bit_idx];
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ff[bit_idx+word_idx*(wl)].d = in.d.d[bit_idx].t;
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ff[bit_idx+word_idx*(wl)].q = data[word_idx].d[bit_idx];
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ff[bit_idx+word_idx*(wl)].reset_B = _reset_mem_BXX[bit_idx+word_idx*(wl)];
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ff[bit_idx+word_idx*(wl)].vdd = supply.vdd;
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ff[bit_idx+word_idx*(wl)].vss = supply.vss;
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// READ: creating the selectors for propagating the right word
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word_to_read_X[word_idx].out[bit_idx] = word_selector_t[bit_idx+word_idx*(wl)].a;
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word_to_read_X[word_idx].out[bit_idx+wl] = word_selector_f[bit_idx+word_idx*(wl)].a;
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word_selector_t[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q;
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word_selector_t[bit_idx+word_idx*(wl)].y = bitselector_t[bit_idx].in[word_idx];
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word_selector_f[bit_idx+word_idx*(wl)].b = ff[bit_idx+word_idx*(wl)].q_B;
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word_selector_f[bit_idx+word_idx*(wl)].y = bitselector_f[bit_idx].in[word_idx];
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bitselector_t[bit_idx].out = output_buf.in.d.d[bit_idx].t;
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bitselector_f[bit_idx].out = output_buf.in.d.d[bit_idx].f;
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bitselector_t[bit_idx].supply = supply;
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bitselector_f[bit_idx].supply = supply;
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)
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)
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}
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}}
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Load Diff
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@ -1,4 +1,4 @@
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#watchall
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watchall
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system "echo '[0] start test'"
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system "echo '----------------------------------------------------------'"
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@ -7,12 +7,18 @@ set t.data[0].d[0] 0
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set t.data[0].d[1] 0
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set t.data[1].d[0] 0
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set t.data[1].d[1] 0
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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set t.out.a 0
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set t.out.v 0
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#set t.registers._in_write.a 0
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set Reset 0
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cycle
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status X
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mode run
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assert-qdi-channel-neutral "t.in" 5
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#mode run
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cycle
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assert-qdi-channel-neutral "t.out" 4
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assert t.data[0].d[0] 0
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assert t.data[0].d[1] 0
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assert t.data[1].d[0] 0
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@ -22,28 +28,44 @@ system "echo '[1] reset completed'"
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system "echo '----------------------------------------------------------'"
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# Set delay config lines
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set t.dly_cfg[0] 1
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set t.dly_cfg[1] 1
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cycle
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system "echo '[2] delay line set'"
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system "echo '----------------------------------------------------------'"
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set-qdi-channel-valid "t.in" 5 3
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# 3 -> 00011 -> writing mode, address 00, word 11
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cycle
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assert-qdi-channel-valid "t.registers._in_write" 4 3
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assert t.registers._clock 0
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assert t.registers._out_encoder[0] 1
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assert t.registers._out_encoder[1] 0
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assert t.registers._out_encoder[2] 0
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assert t.registers._out_encoder[3] 0
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cycle
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assert t.in.a 1
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assert-qdi-channel-neutral "t.out" 4
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set-qdi-channel-neutral "t.in" 5
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cycle
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assert t.registers._clock 1
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assert t.registers.ff_t[0].q 1
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assert t.registers.ff_t[1].q 1
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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system "echo '[3] first writing done'"
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system "echo '----------------------------------------------------------'"
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set-qdi-channel-valid "t.in" 5 16
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# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here)
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cycle
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assert-qdi-channel-valid "t.out" 4 3
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set t.out.v 1
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cycle
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set t.out.a 1
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cycle
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assert t.in.a 1
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set-qdi-channel-neutral "t.in" 5
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cycle
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assert t.registers.ff[0].q 1
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assert t.registers.ff[1].q 1
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assert t.registers.ff[2].q 0
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assert t.registers.ff[3].q 0
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assert-qdi-channel-neutral "t.out" 4
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system "echo '[4] reading done'"
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system "echo '----------------------------------------------------------'"
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