actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0decoder__2d__hybrid_34_79_715_7348_74_4(Iin_d_d0_d0 , Iin_d_d0_d1 , Iin_d_d1_d0 , Iin_d_d1_d1 , Iin_d_d2_d0 , Iin_d_d2_d1 , Iin_d_d3_d0 , Iin_d_d3_d1 , Iin_d_d4_d0 , Iin_d_d4_d1 , Iin_d_d5_d0 , Iin_d_d5_d1 , Iin_d_d6_d0 , Iin_d_d6_d1 , Iin_d_d7_d0 , Iin_d_d7_d1 , Iin_d_d8_d0 , Iin_d_d8_d1 , Iin_d_d9_d0 , Iin_d_d9_d1 , Iin_d_d10_d0 , Iin_d_d10_d1 , Iin_d_d11_d0 , Iin_d_d11_d1 , Iin_d_d12_d0 , Iin_d_d12_d1 , Iin_a , Iin_v , Iout_req_x0 , Iout_req_x1 , Iout_req_x2 , Iout_req_x3 , Iout_req_x4 , Iout_req_x5 , Iout_req_x6 , Iout_req_x7 , Iout_req_x8 , Iout_req_x9 , Iout_req_x10 , Iout_req_x11 , Iout_req_x12 , Iout_req_x13 , Iout_req_x14 , Iout_req_y0 , Iout_req_y1 , Iout_req_y2 , Iout_req_y3 , Iout_req_y4 , Iout_req_y5 , Iout_req_y6 , Iout_req_y7 , Iout_req_y8 , Iout_req_y9 , Iout_req_y10 , Iout_req_y11 , Iout_req_y12 , Iout_req_y13 , Iout_req_y14 , Iout_req_y15 , Iout_req_y16 , Iout_req_y17 , Iout_req_y18 , Iout_req_y19 , Iout_req_y20 , Iout_req_y21 , Iout_req_y22 , Iout_req_y23 , Iout_req_y24 , Iout_req_y25 , Iout_req_y26 , Iout_req_y27 , Iout_req_y28 , Iout_req_y29 , Iout_req_y30 , Iout_req_y31 , Iout_req_y32 , Iout_req_y33 , Iout_req_y34 , Iout_req_y35 , Iout_req_y36 , Iout_req_y37 , Iout_req_y38 , Iout_req_y39 , Iout_req_y40 , Iout_req_y41 , Iout_req_y42 , Iout_req_y43 , Iout_req_y44 , Iout_req_y45 , Iout_req_y46 , Iout_req_y47 , Iout_req_y48 , Iout_req_y49 , Iout_req_y50 , Iout_req_y51 , Iout_req_y52 , Iout_req_y53 , Iout_req_y54 , Iout_req_y55 , Iout_req_y56 , Iout_req_y57 , Iout_req_y58 , Iout_req_y59 , Iout_req_y60 , Iout_req_y61 , Iout_req_y62 , Iout_req_y63 , Iout_req_y64 , Iout_req_y65 , Iout_req_y66 , Iout_req_y67 , Iout_req_y68 , Iout_req_y69 , Iout_req_y70 , Iout_req_y71 , Iout_req_y72 , Iout_req_y73 , Iout_req_y74 , Iout_req_y75 , Iout_req_y76 , Iout_req_y77 , Iout_req_y78 , Iout_req_y79 , Iout_req_y80 , Iout_req_y81 , Iout_req_y82 , Iout_req_y83 , Iout_req_y84 , Iout_req_y85 , Iout_req_y86 , Iout_req_y87 , Iout_req_y88 , Iout_req_y89 , Iout_req_y90 , Iout_req_y91 , Iout_req_y92 , Iout_req_y93 , Iout_req_y94 , Iout_req_y95 , Iout_req_y96 , Iout_req_y97 , Iout_req_y98 , Iout_req_y99 , Iout_req_y100 , Iout_req_y101 , Iout_req_y102 , Iout_req_y103 , Iout_req_y104 , Iout_req_y105 , Iout_req_y106 , Iout_req_y107 , Iout_req_y108 , Iout_req_y109 , Iout_req_y110 , Iout_req_y111 , Iout_req_y112 , Iout_req_y113 , Iout_req_y114 , Iout_req_y115 , Iout_req_y116 , Iout_req_y117 , Iout_req_y118 , Iout_req_y119 , Iout_req_y120 , Iout_req_y121 , Iout_req_y122 , Iout_req_y123 , Iout_req_y124 , Iout_req_y125 , Iout_req_y126 , Iout_req_y127 , Iout_req_y128 , Iout_req_y129 , Iout_req_y130 , Iout_req_y131 , Iout_req_y132 , Iout_req_y133 , Iout_req_y134 , Iout_req_y135 , Iout_req_y136 , Iout_req_y137 , Iout_req_y138 , Iout_req_y139 , Iout_req_y140 , Iout_req_y141 , Iout_req_y142 , Iout_req_y143 , Iout_req_y144 , Iout_req_y145 , Iout_req_y146 , Iout_req_y147 , Iout_req_y148 , Iout_req_y149 , Iout_req_y150 , Iout_req_y151 , Iout_req_y152 , Iout_req_y153 , Iout_req_y154 , Iout_req_y155 , Iout_req_y156 , Iout_req_y157 , Iout_req_y158 , Iout_req_y159 , Iout_req_y160 , Iout_req_y161 , Iout_req_y162 , Iout_req_y163 , Iout_req_y164 , Iout_req_y165 , Iout_req_y166 , Iout_req_y167 , Iout_req_y168 , Iout_req_y169 , Iout_req_y170 , Iout_req_y171 , Iout_req_y172 , Iout_req_y173 , Iout_req_y174 , Iout_req_y175 , Iout_req_y176 , Iout_req_y177 , Iout_req_y178 , Iout_req_y179 , Iout_req_y180 , Iout_req_y181 , Iout_req_y182 , Iout_req_y183 , Iout_req_y184 , Iout_req_y185 , Iout_req_y186 , Iout_req_y187 , Iout_req_y188 , Iout_req_y189 , Iout_req_y190 , Iout_req_y191 , Iout_req_y192 , Iout_req_y193 , Iout_req_y194 , Iout_req_y195 , Iout_req_y196 , Iout_req_y197 , Iout_req_y198 , Iout_req_y199 , Iout_req_y200 , Iout_req_y201 , Iout_req_y202 , Iout_req_y203 , Iout_req_y204 , Iout_req_y205 , Iout_req_y206 , Iout_req_y207 , Iout_req_y208 , Iout_req_y209 , Iout_req_y210 , Iout_req_y211 , Iout_req_y212 , Iout_req_y213 , Iout_req_y214 , Iout_req_y215 , Iout_req_y216 , Iout_req_y217 , Iout_req_y218 , Iout_req_y219 , Iout_req_y
   input vdd;
   input vss;
   input Iin_d_d0_d0 ;
   input Iin_d_d0_d1 ;
   input Iin_d_d1_d0 ;
   input Iin_d_d1_d1 ;
   input Iin_d_d2_d0 ;
   input Iin_d_d2_d1 ;
   input Iin_d_d3_d0 ;
   input Iin_d_d3_d1 ;
   input Iin_d_d4_d0 ;
   input Iin_d_d4_d1 ;
   input Iin_d_d5_d0 ;
   input Iin_d_d5_d1 ;
   input Iin_d_d6_d0 ;
   input Iin_d_d6_d1 ;
   input Iin_d_d7_d0 ;
   input Iin_d_d7_d1 ;
   input Iin_d_d8_d0 ;
   input Iin_d_d8_d1 ;
   input Iin_d_d9_d0 ;
   input Iin_d_d9_d1 ;
   input Iin_d_d10_d0 ;
   input Iin_d_d10_d1 ;
   input Iin_d_d11_d0 ;
   input Iin_d_d11_d1 ;
   input Iin_d_d12_d0 ;
   input Iin_d_d12_d1 ;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   input Idly_cfg0 ;
   input Idly_cfg1 ;
   input Idly_cfg2 ;
   input Idly_cfg3 ;
   input hs_en;
   input ack_disable;
   input Iin_ackB_decoder0 ;
   input Iin_ackB_decoder1 ;
   input Iin_ackB_decoder2 ;
   input Iin_ackB_decoder3 ;
   input Iin_ackB_decoder4 ;
   input Iin_ackB_decoder5 ;
   input Iin_ackB_decoder6 ;
   input Iin_ackB_decoder7 ;
   input Iin_ackB_decoder8 ;
   input Iin_ackB_decoder9 ;
   input Iin_ackB_decoder10 ;
   input Iin_ackB_decoder11 ;
   input Iin_ackB_decoder12 ;
   input Iin_ackB_decoder13 ;
   input Iin_ackB_decoder14 ;
   input Ito_pu0_d_d0 ;
   
   input Ito_pu1_d_d0 ;
   
   input Ito_pu2_d_d0 ;
   
   input Ito_pu3_d_d0 ;
   
   input Ito_pu4_d_d0 ;
   
   input Ito_pu5_d_d0 ;
   
   input Ito_pu6_d_d0 ;
   
   input Ito_pu7_d_d0 ;
   
   input Ito_pu8_d_d0 ;
   
   input Ito_pu9_d_d0 ;
   
   input Ito_pu10_d_d0 ;
   
   input Ito_pu11_d_d0 ;
   
   input Ito_pu12_d_d0 ;
   
   input Ito_pu13_d_d0 ;
   
   input Ito_pu14_d_d0 ;
   
   input reset_B;

// -- signals ---
   output Iout_req_y193 ;
   wire Id_dr_y_out321 ;
   output Iout_req_y312 ;
   output Iout_req_y95 ;
   wire Id_dr_x_out1 ;
   wire Id_dr_y_out168 ;
   wire I_ortree_out ;
   output Iout_req_y225 ;
   wire Id_dr_y_out216 ;
   wire Id_dr_y_out221 ;
   output Iout_req_y317 ;
   output Iout_req_y90 ;
   wire Id_dr_y_out175 ;
   wire Id_dr_y_out262 ;
   wire Iin_d_d1_d1 ;
   wire Id_dr_y_out304 ;
   output Iout_req_y81 ;
   output Iout_req_y22 ;
   wire Id_dr_y_final_refresh_d8_d1 ;
   wire Id_dr_y_out172 ;
   wire Id_dr_y_out269 ;
   wire Id_dr_y_in_d4_d1 ;
   output Iout_req_y127 ;
   wire Id_dr_y_out133 ;
   wire Id_dr_y_out80 ;
   output Iout_req_y253 ;
   wire Id_dr_y_out266 ;
   output Iout_req_y57 ;
   wire Id_dr_y_in_d6_d1 ;
   output Iout_req_x7 ;
   output Iout_req_y282 ;
   wire Id_dr_y_out334 ;
   wire Id_dr_y_in_d3_d0 ;
   output Iout_req_y271 ;
   output Iout_req_y77 ;
   wire Id_dr_y_out280 ;
   output Iout_req_y43 ;
   output Ito_pu1_a ;
   wire Id_dr_y_out31 ;
   wire Id_dr_y_out314 ;
   output Iout_req_y256 ;
   wire Id_dr_y_out23 ;
   output Iout_req_y144 ;
   wire Id_dr_y_out319 ;
   output Iout_req_y236 ;
   wire Id_dr_y_out285 ;
   output Iout_req_y167 ;
   wire Id_dr_y_out53 ;
   output Iout_req_y68 ;
   output Iout_req_y233 ;
   output Iout_req_y76 ;
   wire Id_dr_y_out12 ;
   output Iout_req_y36 ;
   output Iout_req_y208 ;
   wire Idly_cfg0 ;
   wire Id_dr_x_in_d0_d1 ;
   wire Id_dr_x_out2 ;
   wire Id_dr_y_out162 ;
   output Iout_req_x9 ;
   output Iout_req_y243 ;
   wire Id_dr_y_out27 ;
   output Iout_req_y239 ;
   wire Id_dr_y_out180 ;
   wire Id_dr_y_out249 ;
   output Iout_req_y157 ;
   wire Id_dr_y_out56 ;
   output Iout_req_y65 ;
   wire Id_dr_y_in_d5_d0 ;
   output Iout_req_y316 ;
   output Iout_req_y91 ;
   output Iout_req_y71 ;
   wire I_ortree_in9 ;
   wire Id_dr_y_out183 ;
   wire Id_dr_y_out254 ;
   output Iout_req_y141 ;
   wire Id_dr_y_out148 ;
   wire Id_dr_y_out57 ;
   output Iout_req_y285 ;
   wire Id_dr_y_out296 ;
   output Iout_req_y331 ;
   output Iout_req_y108 ;
   wire Id_dr_x_in_d1_d0 ;
   wire Id_dr_y_out328 ;
   output Iout_req_y145 ;
   wire Id_dr_y_out41 ;
   output Iout_req_y171 ;
   wire Id_dr_y_out336 ;
   output Iin_a ;
   wire Id_dr_y_out115 ;
   wire Id_dr_y_out90 ;
   wire Iin_ackB_decoder4 ;
   output Iout_req_y128 ;
   wire Id_dr_y_out206 ;
   wire Id_dr_y_out231 ;
   wire Ito_pu1_d_d0 ;
   output Iout_req_y333 ;
   output Iout_req_y106 ;
   wire Id_dr_y_out6 ;
   wire Id_dr_y_out297 ;
   output Iout_req_x4 ;
   output Iout_req_y309 ;
   wire Id_dr_x_out8 ;
   wire Id_dr_y_out300 ;
   output Iout_req_y329 ;
   output Iout_req_y110 ;
   wire Id_dr_x_out11 ;
   wire Id_dr_y_out210 ;
   wire Id_dr_y_out219 ;
   output Iout_req_y206 ;
   wire Id_dr_y_out208 ;
   wire Id_dr_y_out229 ;
   output Iout_req_y336 ;
   output Iout_req_y119 ;
   wire Id_dr_x_final_refresh_d2_d1 ;
   wire Id_dr_y_out313 ;
   output Iout_req_y138 ;
   wire Id_dr_y_out114 ;
   wire Id_dr_y_out91 ;
   wire Id_dr_y_final_refresh_d5_d1 ;
   output Iout_req_y27 ;
   output Iout_req_y152 ;
   wire Id_dr_y_out303 ;
   output Iout_req_y54 ;
   output Iout_req_y198 ;
   wire reset_B;
   wire Id_dr_y_out295 ;
   output Iout_req_y163 ;
   wire Iin_d_d6_d0 ;
   output Iout_req_y263 ;
   wire Id_dr_y_out38 ;
   output Iout_req_y2 ;
   output Iout_req_y151 ;
   wire Id_dr_y_out158 ;
   wire Id_dr_y_out2 ;
   output Iout_req_y86 ;
   wire Id_dr_x_in_d2_d1 ;
   wire Id_dr_y_out207 ;
   wire Id_dr_y_out230 ;
   wire Ito_pu3_d_d0 ;
   output Iout_req_y161 ;
   wire Id_dr_x_final_refresh_d3_d0 ;
   wire Id_dr_y_out279 ;
   output Iout_req_y82 ;
   wire Id_dr_x_in_d1_d1 ;
   wire Id_dr_y_out167 ;
   output Iout_req_y272 ;
   wire Id_dr_y_out126 ;
   wire Id_dr_y_out87 ;
   output Iout_req_y23 ;
   output Iout_req_y323 ;
   output Iout_req_y100 ;
   wire Id_dr_y_out32 ;
   output Iout_req_y18 ;
   wire Iin_d_d8_d0 ;
   output Iout_req_y197 ;
   wire Id_dr_y_out273 ;
   output Iout_req_y169 ;
   wire Iin_ackB_decoder13 ;
   wire Id_dr_y_out338 ;
   wire Id_dr_y_out347 ;
   output Iout_req_y210 ;
   wire Id_dr_y_out144 ;
   wire Id_dr_y_out69 ;
   output Iout_req_y5 ;
   wire Id_dr_y_in_d0_d0 ;
   output Iout_req_y142 ;
   wire Id_dr_y_out311 ;
   wire Iin_d_d6_d1 ;
   output Iout_req_y300 ;
   wire Id_dr_y_out161 ;
   output Iout_req_y313 ;
   output Iout_req_y94 ;
   wire Id_dr_y_out54 ;
   output Iout_req_y67 ;
   output Iout_req_y180 ;
   output Iout_req_y58 ;
   output Iout_req_y291 ;
   wire Id_dr_y_out48 ;
   wire Iin_ackB_decoder7 ;
   output Iout_req_y150 ;
   wire I_ortree_in10 ;
   wire Id_dr_y_out213 ;
   wire Id_dr_y_out224 ;
   wire Id_dr_y_in_d8_d1 ;
   wire Id_dr_y_out268 ;
   output Iout_req_y257 ;
   wire Id_dr_y_final_refresh_d3_d1 ;
   wire Id_dr_y_out204 ;
   wire Id_dr_y_out225 ;
   output Iout_req_y304 ;
   wire Idly_out ;
   wire Id_dr_y_out174 ;
   wire Id_dr_y_out263 ;
   output Iout_req_y209 ;
   wire Id_dr_y_out42 ;
   output Iout_req_y295 ;
   wire Id_dr_y_out33 ;
   wire Id_dr_y_out316 ;
   output Iout_req_y155 ;
   wire Id_dr_y_final_refresh_d6_d1 ;
   wire Id_dr_y_out264 ;
   output Iout_req_y251 ;
   wire Id_dr_y_out36 ;
   wire Id_dr_y_out11 ;
   wire Id_dr_y_out165 ;
   output Iout_req_y63 ;
   output Iout_req_y278 ;
   wire Id_dr_y_out8 ;
   output Iout_req_y250 ;
   output Iout_req_y133 ;
   wire Id_dr_y_out132 ;
   wire Id_dr_y_out73 ;
   output Iout_req_y9 ;
   output Iout_req_y165 ;
   wire Id_dr_y_out191 ;
   wire Id_dr_y_out246 ;
   output Iout_req_y230 ;
   wire Id_dr_y_out259 ;
   output Iout_req_y229 ;
   wire Id_dr_y_final_refresh_d4_d0 ;
   wire Id_dr_y_out29 ;
   wire Id_dr_y_out320 ;
   output Iout_req_y246 ;
   wire Id_dr_y_out187 ;
   wire Id_dr_y_out242 ;
   output Iout_req_x1 ;
   wire Ito_pu13_d_d0 ;
   output Iout_req_y322 ;
   output Iout_req_y101 ;
   wire Id_dr_y_out13 ;
   output Iout_req_y296 ;
   output Iout_req_y74 ;
   wire I_ortree_in7 ;
   output Iout_req_y38 ;
   output Iout_req_y228 ;
   wire Id_dr_y_out312 ;
   output Iout_req_y264 ;
   wire Id_dr_y_out113 ;
   wire Id_dr_y_out92 ;
   wire Ito_pu5_d_d0 ;
   output Iout_req_y315 ;
   output Iout_req_y92 ;
   wire I_ortree_in4 ;
   wire Id_dr_y_out260 ;
   output Iout_req_x12 ;
   output Iout_req_y218 ;
   wire I_ortree_in2 ;
   wire Id_dr_y_out276 ;
   wire Iin_d_d10_d1 ;
   output Iout_req_y85 ;
   wire Iack_mux_b ;
   wire Id_dr_y_out9 ;
   wire Id_dr_y_out195 ;
   wire Id_dr_y_out234 ;
   output Iout_req_y319 ;
   output Iout_req_y88 ;
   output Iout_req_y28 ;
   wire Id_dr_y_in_d1_d1 ;
   output Iout_req_y153 ;
   wire Id_dr_y_out153 ;
   wire Id_dr_y_out52 ;
   output Iout_req_y314 ;
   output Iout_req_y93 ;
   wire Id_dr_x_final_refresh_d1_d0 ;
   wire Id_dr_y_out335 ;
   wire Id_dr_y_in_d2_d0 ;
   output Iout_req_y192 ;
   wire Id_dr_y_out342 ;
   wire Iin_d_d12_d1 ;
   output Iout_req_y212 ;
   wire Id_dr_y_out181 ;
   wire Id_dr_y_out256 ;
   output Iout_req_y207 ;
   wire Iin_ackB_decoder5 ;
   output Iout_req_y123 ;
   wire Id_dr_y_out289 ;
   output Iout_req_y217 ;
   wire Id_dr_y_out128 ;
   wire Id_dr_y_out85 ;
   output Iout_req_y21 ;
   output Iout_req_y174 ;
   wire Id_dr_y_out145 ;
   wire Id_dr_y_out60 ;
   output Iout_req_y64 ;
   output Iout_req_y147 ;
   wire Id_dr_y_final_refresh_d2_d1 ;
   wire Id_dr_x_out6 ;
   wire Iin_d_d7_d0 ;
   output Iout_req_y199 ;
   wire Id_dr_y_out28 ;
   wire Ito_pu9_d_d0 ;
   wire Iin_ackB_decoder6 ;
   wire Id_dr_y_out185 ;
   wire Id_dr_y_out244 ;
   output Iout_req_y335 ;
   output Iout_req_y104 ;
   wire Id_dr_y_out110 ;
   wire Id_dr_y_out103 ;
   output Iout_req_y39 ;
   output Iout_req_y301 ;
   wire Id_dr_y_out130 ;
   wire Id_dr_y_out75 ;
   output Iout_req_y11 ;
   output Iout_req_y288 ;
   wire Id_dr_y_out45 ;
   output Iout_req_y137 ;
   wire Id_dr_y_out315 ;
   output Iout_req_x11 ;
   output Iout_req_y241 ;
   wire Id_dr_y_out120 ;
   wire Id_dr_y_out93 ;
   output Iout_req_y29 ;
   output Iout_req_y160 ;
   wire Id_dr_y_out203 ;
   wire Id_dr_y_out226 ;
   output Iout_req_y46 ;
   output Iout_req_y149 ;
   wire Id_dr_y_out19 ;
   output Iout_req_y183 ;
   wire Id_dr_y_out35 ;
   wire Iin_ackB_decoder0 ;
   wire Id_dr_y_out310 ;
   output Iout_req_y255 ;
   wire Id_dr_y_out337 ;
   output Iout_req_y0 ;
   output Iout_req_y59 ;
   output Iout_req_y258 ;
   wire Id_dr_y_out299 ;
   wire Id_dr_y_out40 ;
   output Iout_req_y126 ;
   wire Id_dr_y_out265 ;
   output Iout_req_y270 ;
   wire Id_dr_y_out150 ;
   wire Id_dr_y_out63 ;
   output Iout_req_y249 ;
   wire Id_dr_y_out142 ;
   wire Id_dr_y_out71 ;
   wire Idly_in ;
   output Iout_req_y7 ;
   output Iout_req_y61 ;
   output Iout_req_y164 ;
   wire Id_dr_y_out152 ;
   wire Id_dr_y_out61 ;
   output Iout_req_y42 ;
   wire Id_dr_y_in_d7_d1 ;
   output Iout_req_y339 ;
   output Iout_req_y116 ;
   wire Id_dr_y_out135 ;
   wire Id_dr_y_out78 ;
   wire Id_dr_y_out293 ;
   output Iout_req_y1 ;
   output Iout_req_y172 ;
   wire Id_dr_y_final_refresh_d8_d0 ;
   wire Id_dr_y_out339 ;
   wire Id_dr_y_out346 ;
   output Iout_req_y186 ;
   wire Id_dr_y_out125 ;
   wire Id_dr_y_out88 ;
   wire Id_dr_x_in_d2_d0 ;
   output Iout_req_y346 ;
   wire Id_dr_y_out138 ;
   wire Id_dr_y_out67 ;
   output Iout_req_y3 ;
   output Iout_req_y345 ;
   wire Id_dr_y_out271 ;
   wire Ito_pu14_d_d0 ;
   output Iout_req_y140 ;
   wire Id_dr_y_out147 ;
   wire Id_dr_y_out58 ;
   output Iout_req_y154 ;
   wire Id_dr_y_out281 ;
   output Iout_req_y52 ;
   output Iout_req_y178 ;
   wire Iin_ackB_decoder3 ;
   wire Id_dr_y_out215 ;
   wire Id_dr_y_out222 ;
   output Iout_req_y60 ;
   output Iout_req_y260 ;
   output Iout_req_y289 ;
   wire Id_dr_y_out343 ;
   wire Iin_d_d7_d1 ;
   output Iout_req_y235 ;
   wire Id_dr_y_out288 ;
   output Iout_req_y238 ;
   wire Id_dr_y_out287 ;
   output Iout_req_y179 ;
   wire Id_dr_y_out146 ;
   wire Id_dr_y_out59 ;
   wire Iin_d_d1_d0 ;
   wire Id_dr_y_out332 ;
   output Iout_req_y189 ;
   wire Id_dr_y_out105 ;
   wire Id_dr_y_out100 ;
   wire Ito_pu2_d_d0 ;
   wire Id_dr_y_out139 ;
   wire Id_dr_y_out66 ;
   wire Iin_d_d9_d0 ;
   output Iout_req_y224 ;
   wire Id_dr_y_out267 ;
   output Iout_req_x6 ;
   output Ito_pu11_a ;
   output Iout_req_y311 ;
   wire I_ortree_in8 ;
   wire Id_dr_y_out309 ;
   wire Id_dr_y_in_d1_d0 ;
   output Iout_req_y318 ;
   output Iout_req_y89 ;
   wire Id_dr_y_out292 ;
   output Iout_req_y136 ;
   wire I_ortree_in14 ;
   wire Id_dr_y_out325 ;
   output Iout_req_y299 ;
   wire Id_dr_y_out333 ;
   wire Iin_d_d2_d1 ;
   wire Id_dr_y_in_d2_d1 ;
   output Iout_req_y275 ;
   wire Iin_ackB_decoder9 ;
   wire Id_dr_y_out282 ;
   output Iout_req_y55 ;
   output Iout_req_y303 ;
   wire Iin_ackB_decoder2 ;
   wire Id_dr_y_out330 ;
   output Iout_req_y341 ;
   output Iout_req_y114 ;
   wire Id_dr_y_out22 ;
   output Iout_req_x5 ;
   wire Ito_pu12_d_d0 ;
   output Iout_req_y280 ;
   wire Id_dr_y_out39 ;
   wire I_ortree_in3 ;
   output Iout_req_y205 ;
   wire Id_dr_y_out117 ;
   wire Id_dr_y_out96 ;
   wire Id_dr_y_in_d5_d1 ;
   output Iout_req_y83 ;
   output Iout_req_y80 ;
   wire I_ortree_in13 ;
   output Iout_req_y8 ;
   wire Id_dr_y_in_d8_d0 ;
   output Iout_req_y190 ;
   wire Id_dr_y_out182 ;
   wire Id_dr_y_out255 ;
   wire Iin_d_d3_d1 ;
   output Iout_req_y121 ;
   wire Id_dr_y_final_refresh_d5_d0 ;
   wire Id_dr_y_out329 ;
   output Iout_req_y146 ;
   wire Id_dr_x_final_refresh_d1_d1 ;
   wire Id_dr_y_out257 ;
   output Iout_req_x0 ;
   output Iout_req_y293 ;
   wire Id_dr_y_out140 ;
   wire Id_dr_y_out65 ;
   output Iout_req_y173 ;
   output Iout_req_y215 ;
   wire Id_dr_y_final_refresh_d7_d1 ;
   wire Id_dr_y_out184 ;
   wire Id_dr_y_out253 ;
   output Iout_req_y326 ;
   output Iout_req_y97 ;
   wire Id_dr_y_out166 ;
   output Iout_req_y305 ;
   wire Id_dr_x_in_d3_d0 ;
   output Iout_req_y24 ;
   output Iout_req_y284 ;
   wire Id_dr_y_out119 ;
   wire Id_dr_y_out94 ;
   wire Id_dr_y_final_refresh_d0_d1 ;
   output Iout_req_y334 ;
   output Iout_req_y105 ;
   wire Id_dr_y_out199 ;
   wire Id_dr_y_out238 ;
   output Iout_req_y223 ;
   wire Id_dr_y_out308 ;
   wire Iin_d_d9_d1 ;
   output Iout_req_y200 ;
   wire Id_dr_y_out109 ;
   wire Id_dr_y_out104 ;
   output Iout_req_y226 ;
   wire Iin_ackB_decoder10 ;
   wire Id_dr_y_out290 ;
   output Ito_pu6_a ;
   output Iout_req_y170 ;
   wire Iin_ackB_decoder11 ;
   wire Id_dr_y_out302 ;
   output Ito_pu7_a ;
   output Iout_req_y267 ;
   wire Id_dr_y_final_refresh_d1_d1 ;
   wire Id_dr_y_out190 ;
   wire Id_dr_y_out247 ;
   output Iout_req_y47 ;
   output Iout_req_y143 ;
   wire Id_dr_y_out272 ;
   output Iout_req_y327 ;
   output Iout_req_y96 ;
   wire Id_dr_y_out294 ;
   wire Id_dr_y_out164 ;
   wire Id_dr_y_out44 ;
   output Iout_req_y69 ;
   output Iout_req_y175 ;
   wire Id_dr_y_out1 ;
   wire Id_dr_y_out20 ;
   output Iout_req_y213 ;
   wire Id_dr_x_out4 ;
   wire Id_dr_y_out5 ;
   output Iout_req_y4 ;
   output Iout_req_y227 ;
   wire Id_dr_y_final_refresh_d3_d0 ;
   wire Ivtree_y_out ;
   wire Id_dr_y_out274 ;
   output Iout_req_y214 ;
   wire Id_dr_y_final_refresh_d7_d0 ;
   wire Id_dr_y_out306 ;
   output Iout_req_x14 ;
   output Iout_req_y216 ;
   wire Id_dr_x_out7 ;
   wire Id_dr_y_out169 ;
   output Iout_req_y281 ;
   wire Id_dr_y_out201 ;
   wire Id_dr_y_out228 ;
   output Iout_req_x3 ;
   output Iout_req_y286 ;
   output Iout_req_y70 ;
   wire Id_dr_y_out43 ;
   output Iout_req_y191 ;
   wire Id_dr_y_out151 ;
   wire Id_dr_y_out62 ;
   wire Id_dr_x_in_d0_d0 ;
   wire ack_disable;
   output Iout_req_y196 ;
   wire Id_dr_y_out277 ;
   output Iout_req_y158 ;
   output Iout_req_y79 ;
   wire Id_dr_y_out278 ;
   output Iout_req_y48 ;
   output Ito_pu12_a ;
   output Iout_req_y252 ;
   wire Id_dr_y_out7 ;
   wire Id_dr_y_out193 ;
   wire Id_dr_y_out236 ;
   output Iout_req_y135 ;
   wire Iin_ackB_decoder1 ;
   wire Id_dr_x_out5 ;
   wire Id_dr_y_out170 ;
   output Iout_req_y6 ;
   wire Iin_d_d8_d1 ;
   output Iout_req_y177 ;
   wire I_ortree_in11 ;
   wire Id_dr_y_out286 ;
   wire Iin_d_d2_d0 ;
   output Iout_req_y131 ;
   wire Id_dr_y_out270 ;
   output Iout_req_y203 ;
   wire Id_dr_y_out118 ;
   wire Id_dr_y_out95 ;
   output Iout_req_y31 ;
   output Iout_req_y240 ;
   wire Id_dr_y_out10 ;
   wire Id_dr_y_out163 ;
   wire Ito_pu6_d_d0 ;
   output Iout_req_y245 ;
   wire I_ortree_in5 ;
   wire Id_dr_y_out326 ;
   output Iout_req_y277 ;
   wire Id_dr_y_out192 ;
   wire Id_dr_y_out245 ;
   output Iout_req_y49 ;
   output Iout_req_x13 ;
   output Iout_req_y247 ;
   wire Id_dr_y_out106 ;
   wire Id_dr_y_out99 ;
   wire Iin_ackB_decoder14 ;
   output Iout_req_y35 ;
   output Iout_req_y265 ;
   wire Id_dr_y_out112 ;
   wire Id_dr_y_out101 ;
   wire Id_dr_x_out0 ;
   output Iout_req_y37 ;
   output Iout_req_y45 ;
   output Iout_req_y182 ;
   wire Id_dr_y_out143 ;
   wire Id_dr_y_out70 ;
   output Iout_req_y56 ;
   output Iout_req_y269 ;
   wire Id_dr_x_out12 ;
   wire Id_dr_y_out18 ;
   output Iout_req_y41 ;
   output Iout_req_y325 ;
   output Iout_req_y98 ;
   wire Id_dr_y_out26 ;
   wire Iin_d_d10_d0 ;
   output Iout_req_y156 ;
   wire Id_dr_y_out124 ;
   wire Id_dr_y_out81 ;
   wire Ivtree_x_out ;
   output Iout_req_y17 ;
   output Iout_req_y50 ;
   output Iout_req_y321 ;
   output Iout_req_y102 ;
   wire Id_dr_y_out327 ;
   output Ito_pu8_a ;
   output Iout_req_y181 ;
   wire Id_dr_y_out344 ;
   wire Iin_d_d12_d0 ;
   output Iout_req_y308 ;
   wire Id_dr_y_out211 ;
   wire Id_dr_y_out218 ;
   output Iout_req_y234 ;
   wire Id_dr_y_out324 ;
   output Iout_req_y185 ;
   wire Id_dr_y_out318 ;
   wire Ito_pu7_d_d0 ;
   output Iout_req_y268 ;
   wire Id_dr_y_out3 ;
   wire Id_dr_y_out171 ;
   wire Id_dr_y_out186 ;
   wire Id_dr_y_out243 ;
   output Iout_req_y188 ;
   wire Id_dr_x_out10 ;
   wire Id_dr_y_out30 ;
   output Iout_req_y20 ;
   output Iout_req_y125 ;
   wire Id_dr_y_out17 ;
   output Iout_req_y244 ;
   wire Id_dr_y_out341 ;
   output Iout_req_y168 ;
   wire Id_dr_y_out141 ;
   wire Id_dr_y_out72 ;
   output Iout_req_y159 ;
   wire Id_dr_y_out283 ;
   output Iin_v ;
   output Iout_req_x2 ;
   output Ito_pu2_a ;
   output Iout_req_y120 ;
   wire Id_dr_y_out305 ;
   output Ito_pu4_a ;
   output Iout_req_y332 ;
   output Iout_req_y107 ;
   wire Iack_block_y ;
   wire Id_dr_y_out331 ;
   output Iout_req_y302 ;
   wire Id_dr_y_out46 ;
   wire Ito_pu8_d_d0 ;
   output Iout_req_y134 ;
   wire Id_dr_y_out134 ;
   wire Id_dr_y_out79 ;
   output Iout_req_y15 ;
   output Iout_req_y237 ;
   wire Id_dr_y_out129 ;
   wire Id_dr_y_out76 ;
   wire Iin_ackB_decoder8 ;
   wire Id_dr_y_out212 ;
   wire Id_dr_y_out217 ;
   wire Iin_d_d11_d0 ;
   output Ito_pu14_a ;
   wire Ito_pu4_d_d0 ;
   output Iout_req_y232 ;
   wire Id_dr_y_out155 ;
   wire Id_dr_y_out50 ;
   wire Id_dr_x_final_refresh_d0_d0 ;
   output Iout_req_y219 ;
   wire Id_dr_y_out47 ;
   output Iout_req_y166 ;
   wire Id_dr_y_out108 ;
   wire Id_dr_y_out97 ;
   output Iout_req_y33 ;
   output Iout_req_y40 ;
   output Iout_req_y231 ;
   wire Id_dr_y_out122 ;
   wire Id_dr_y_out83 ;
   output Iout_req_y19 ;
   wire Id_dr_y_in_d6_d0 ;
   output Iout_req_y307 ;
   wire I_ortree_in0 ;
   output Iout_req_y176 ;
   wire Id_dr_y_out178 ;
   wire Id_dr_y_out251 ;
   output Iout_req_y62 ;
   wire Ito_pu0_d_d0 ;
   output Iout_req_y184 ;
   wire Id_dr_y_out14 ;
   output Iout_req_y34 ;
   wire Id_dr_y_out156 ;
   wire Id_dr_y_out49 ;
   output Iout_req_y274 ;
   output Iout_req_y283 ;
   wire hs_enB ;
   wire Id_dr_y_out205 ;
   wire Id_dr_y_out232 ;
   wire Id_dr_x_out14 ;
   output Iout_req_y328 ;
   output Iout_req_y111 ;
   output Iout_req_y273 ;
   wire Id_dr_y_out317 ;
   output Iout_req_y53 ;
   wire Iin_d_d4_d0 ;
   output Iout_req_y261 ;
   wire Id_dr_y_out15 ;
   wire Iin_d_d5_d0 ;
   output Ito_pu10_a ;
   output Ito_pu9_a ;
   output Iout_req_y338 ;
   output Iout_req_y117 ;
   wire Id_dr_y_out258 ;
   output Iout_req_y259 ;
   wire Id_dr_y_out173 ;
   wire Id_dr_y_out214 ;
   wire Id_dr_y_out223 ;
   wire Iin_d_d4_d1 ;
   wire Id_dr_y_out284 ;
   output Iout_req_y187 ;
   wire Id_dr_y_out21 ;
   output Iout_req_y330 ;
   output Iout_req_y109 ;
   wire Id_dr_y_out136 ;
   wire Id_dr_y_out77 ;
   output Iout_req_y13 ;
   output Iout_req_y211 ;
   wire Id_dr_y_out116 ;
   wire Id_dr_y_out89 ;
   output Iout_req_y25 ;
   output Iout_req_y195 ;
   wire Id_dr_y_out200 ;
   wire Id_dr_y_out237 ;
   output Iout_req_y242 ;
   wire Id_dr_y_out127 ;
   wire Id_dr_y_out86 ;
   wire Idly_cfg3 ;
   wire Id_dr_y_final_refresh_d2_d0 ;
   output Iout_req_y162 ;
   wire Id_dr_y_out275 ;
   output Iout_req_y44 ;
   output Ito_pu13_a ;
   output Iout_req_y298 ;
   wire Iack_mux_a ;
   wire hs_en;
   wire Id_dr_y_out25 ;
   output Iout_req_y310 ;
   wire Id_dr_y_out137 ;
   wire Id_dr_y_out68 ;
   wire Id_dr_x_final_refresh_d2_d0 ;
   output Iout_req_y337 ;
   output Iout_req_y118 ;
   wire Id_dr_y_out107 ;
   wire Id_dr_y_out98 ;
   wire Iack_block_b ;
   output Iout_req_y194 ;
   wire Id_dr_y_out194 ;
   wire Id_dr_y_out235 ;
   output Iout_req_y130 ;
   wire Id_dr_x_out13 ;
   wire Id_dr_y_out24 ;
   output Iout_req_y297 ;
   wire Id_dr_y_out154 ;
   wire Id_dr_y_out51 ;
   wire Id_dr_x_final_refresh_d3_d1 ;
   wire Id_dr_y_out160 ;
   output Ito_pu3_a ;
   output Iout_req_y343 ;
   output Iout_req_y112 ;
   wire Idly_cfg2 ;
   wire Id_dr_x_out9 ;
   wire Id_dr_y_out196 ;
   wire Id_dr_y_out233 ;
   output Iout_req_y342 ;
   output Iout_req_y113 ;
   wire Id_dr_y_out176 ;
   wire Id_dr_y_out261 ;
   output Iout_req_y204 ;
   wire Id_dr_y_out298 ;
   output Iout_req_y276 ;
   output Iout_req_y78 ;
   output Iout_req_y10 ;
   output Iout_req_y294 ;
   wire Id_dr_y_final_refresh_d6_d0 ;
   wire Id_dr_x_final_refresh_d0_d1 ;
   output Iout_req_y12 ;
   output Iout_req_y340 ;
   output Iout_req_y115 ;
   wire Id_dr_y_out202 ;
   wire Id_dr_y_out227 ;
   output Iout_req_y344 ;
   output Iout_req_y73 ;
   wire Id_dr_y_final_refresh_d0_d0 ;
   wire Id_dr_y_final_refresh_d1_d0 ;
   wire Id_dr_y_out177 ;
   wire Id_dr_y_out252 ;
   output Iout_req_y122 ;
   wire Id_dr_y_out34 ;
   wire Id_dr_y_out0 ;
   output Iout_req_y16 ;
   output Ito_pu5_a ;
   output Iout_req_y262 ;
   output Iout_req_y14 ;
   wire Iin_d_d3_d0 ;
   wire Iin_d_d0_d1 ;
   output Iout_req_y290 ;
   wire Id_dr_y_out157 ;
   output Iout_req_y279 ;
   wire Id_dr_y_out37 ;
   wire Id_dr_y_out4 ;
   output Iout_req_y26 ;
   output Iout_req_y51 ;
   wire Iin_d_d11_d1 ;
   output Iout_req_y221 ;
   wire Id_dr_y_out55 ;
   output Iout_req_y66 ;
   output Iout_req_y287 ;
   wire Iin_ackB_decoder12 ;
   wire Id_dr_y_out307 ;
   output Iout_req_y129 ;
   wire Id_dr_y_out123 ;
   wire Id_dr_y_out82 ;
   wire Id_dr_y_final_refresh_d4_d1 ;
   output Iout_req_y202 ;
   output Iout_req_y30 ;
   wire Ito_pu11_d_d0 ;
   output Iout_req_y254 ;
   wire Id_dr_y_out198 ;
   wire Id_dr_y_out239 ;
   output Iout_req_y347 ;
   wire Id_dr_x_in_d3_d1 ;
   wire Id_dr_y_out197 ;
   wire Id_dr_y_out240 ;
   output Iout_req_y139 ;
   wire Idly_cfg1 ;
   wire Id_dr_y_out301 ;
   output Iout_req_y84 ;
   output Iout_req_y72 ;
   wire Id_dr_y_out16 ;
   output Iout_req_y32 ;
   wire Id_dr_y_in_d0_d1 ;
   output Iout_req_y292 ;
   wire Id_dr_x_out3 ;
   wire Id_dr_y_out188 ;
   wire Id_dr_y_out241 ;
   output Iout_req_x8 ;
   output Iout_req_y222 ;
   wire Id_dr_y_out111 ;
   wire Id_dr_y_out102 ;
   wire I_ortree_in1 ;
   wire Id_dr_y_in_d4_d0 ;
   output Iout_req_y148 ;
   wire Id_dr_y_out340 ;
   wire Id_dr_y_out345 ;
   wire Ito_pu10_d_d0 ;
   output Iout_req_y124 ;
   output Iout_req_y75 ;
   wire Id_dr_y_out179 ;
   wire Id_dr_y_out250 ;
   wire Id_dr_y_out131 ;
   wire Id_dr_y_out74 ;
   output Iout_req_y248 ;
   wire Id_dr_y_out291 ;
   output Iout_req_y87 ;
   wire Id_dr_y_out323 ;
   output Iout_req_y306 ;
   wire Id_dr_y_out189 ;
   wire Id_dr_y_out248 ;
   output Iout_req_y320 ;
   output Iout_req_y103 ;
   wire Id_dr_y_in_d3_d1 ;
   output Ito_pu0_a ;
   output Iout_req_y132 ;
   wire Id_dr_y_out149 ;
   wire Id_dr_y_out64 ;
   wire Id_dr_y_in_d7_d0 ;
   output Iout_req_y201 ;
   wire I_ortree_in12 ;
   wire Id_dr_y_out209 ;
   wire Id_dr_y_out220 ;
   wire Iin_d_d0_d0 ;
   output Iout_req_y266 ;
   wire Id_dr_y_out121 ;
   wire Id_dr_y_out84 ;
   output Iout_req_y324 ;
   output Iout_req_y99 ;
   wire Id_dr_y_out159 ;
   wire I_ortree_in6 ;
   wire Iin_d_d5_d1 ;
   output Iout_req_x10 ;
   output Iout_req_y220 ;
   wire I_reset_BX0 ;
   wire Id_dr_y_out322 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0delayprog_34_4 Idly  (.out(Idly_out ), .in(Idly_in ), .Is0 (Idly_cfg0 ), .Is1 (Idly_cfg1 ), .Is2 (Idly_cfg2 ), .Is3 (Idly_cfg3 ), .vdd(vdd), .vss(vss));
AND2_X1 Iack_block  (.y(Iack_block_y ), .a(Idly_out ), .b(Iack_block_b ), .vdd(vdd), .vss(vss));
MUX2_X1 Iack_mux  (.y(Idly_in ), .a(Iack_mux_a ), .b(Iack_mux_b ), .s(hs_en), .vdd(vdd), .vss(vss));
INV_X4 Ihs_inv  (.y(hs_enB), .a(hs_en), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_39_4 Ivtree_y  (.Iin_d0_d0 (Id_dr_y_final_refresh_d0_d0 ), .Iin_d0_d1 (Id_dr_y_final_refresh_d0_d1 ), .Iin_d1_d0 (Id_dr_y_final_refresh_d1_d0 ), .Iin_d1_d1 (Id_dr_y_final_refresh_d1_d1 ), .Iin_d2_d0 (Id_dr_y_final_refresh_d2_d0 ), .Iin_d2_d1 (Id_dr_y_final_refresh_d2_d1 ), .Iin_d3_d0 (Id_dr_y_final_refresh_d3_d0 ), .Iin_d3_d1 (Id_dr_y_final_refresh_d3_d1 ), .Iin_d4_d0 (Id_dr_y_final_refresh_d4_d0 ), .Iin_d4_d1 (Id_dr_y_final_refresh_d4_d1 ), .Iin_d5_d0 (Id_dr_y_final_refresh_d5_d0 ), .Iin_d5_d1 (Id_dr_y_final_refresh_d5_d1 ), .Iin_d6_d0 (Id_dr_y_final_refresh_d6_d0 ), .Iin_d6_d1 (Id_dr_y_final_refresh_d6_d1 ), .Iin_d7_d0 (Id_dr_y_final_refresh_d7_d0 ), .Iin_d7_d1 (Id_dr_y_final_refresh_d7_d1 ), .Iin_d8_d0 (Id_dr_y_final_refresh_d8_d0 ), .Iin_d8_d1 (Id_dr_y_final_refresh_d8_d1 ), .out(Ivtree_y_out ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 Ireset_sb  (.in(reset_B), .Iout0 (I_reset_BX0 ), .vdd(vdd), .vss(vss));
A_2C_B_X1 Ivalid_Cel  (.y(Iack_mux_a ), .c1(Ivtree_x_out ), .c2(Ivtree_y_out ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs0  (.y(I_ortree_in0 ), .a(Iin_ackB_decoder0 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs1  (.y(I_ortree_in1 ), .a(Iin_ackB_decoder1 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs2  (.y(I_ortree_in2 ), .a(Iin_ackB_decoder2 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs3  (.y(I_ortree_in3 ), .a(Iin_ackB_decoder3 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs4  (.y(I_ortree_in4 ), .a(Iin_ackB_decoder4 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs5  (.y(I_ortree_in5 ), .a(Iin_ackB_decoder5 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs6  (.y(I_ortree_in6 ), .a(Iin_ackB_decoder6 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs7  (.y(I_ortree_in7 ), .a(Iin_ackB_decoder7 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs8  (.y(I_ortree_in8 ), .a(Iin_ackB_decoder8 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs9  (.y(I_ortree_in9 ), .a(Iin_ackB_decoder9 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs10  (.y(I_ortree_in10 ), .a(Iin_ackB_decoder10 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs11  (.y(I_ortree_in11 ), .a(Iin_ackB_decoder11 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs12  (.y(I_ortree_in12 ), .a(Iin_ackB_decoder12 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs13  (.y(I_ortree_in13 ), .a(Iin_ackB_decoder13 ), .vdd(vdd), .vss(vss));
INV_X1 Iout_ack_invs14  (.y(I_ortree_in14 ), .a(Iin_ackB_decoder14 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_34_715_4 Id_dr_x  (.Iin_d0_d0 (Id_dr_x_in_d0_d0 ), .Iin_d0_d1 (Id_dr_x_in_d0_d1 ), .Iin_d1_d0 (Id_dr_x_in_d1_d0 ), .Iin_d1_d1 (Id_dr_x_in_d1_d1 ), .Iin_d2_d0 (Id_dr_x_in_d2_d0 ), .Iin_d2_d1 (Id_dr_x_in_d2_d1 ), .Iin_d3_d0 (Id_dr_x_in_d3_d0 ), .Iin_d3_d1 (Id_dr_x_in_d3_d1 ), .Iout0 (Id_dr_x_out0 ), .Iout1 (Id_dr_x_out1 ), .Iout2 (Id_dr_x_out2 ), .Iout3 (Id_dr_x_out3 ), .Iout4 (Id_dr_x_out4 ), .Iout5 (Id_dr_x_out5 ), .Iout6 (Id_dr_x_out6 ), .Iout7 (Id_dr_x_out7 ), .Iout8 (Id_dr_x_out8 ), .Iout9 (Id_dr_x_out9 ), .Iout10 (Id_dr_x_out10 ), .Iout11 (Id_dr_x_out11 ), .Iout12 (Id_dr_x_out12 ), .Iout13 (Id_dr_x_out13 ), .Iout14 (Id_dr_x_out14 ), .Ifinal_refresh_d0_d0 (Id_dr_x_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Id_dr_x_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Id_dr_x_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Id_dr_x_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Id_dr_x_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Id_dr_x_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Id_dr_x_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Id_dr_x_final_refresh_d3_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_3348_747_4 Id_dr_yX  (.Iin0 (Id_dr_y_out0 ), .Iin1 (Id_dr_y_out1 ), .Iin2 (Id_dr_y_out2 ), .Iin3 (Id_dr_y_out3 ), .Iin4 (Id_dr_y_out4 ), .Iin5 (Id_dr_y_out5 ), .Iin6 (Id_dr_y_out6 ), .Iin7 (Id_dr_y_out7 ), .Iin8 (Id_dr_y_out8 ), .Iin9 (Id_dr_y_out9 ), .Iin10 (Id_dr_y_out10 ), .Iin11 (Id_dr_y_out11 ), .Iin12 (Id_dr_y_out12 ), .Iin13 (Id_dr_y_out13 ), .Iin14 (Id_dr_y_out14 ), .Iin15 (Id_dr_y_out15 ), .Iin16 (Id_dr_y_out16 ), .Iin17 (Id_dr_y_out17 ), .Iin18 (Id_dr_y_out18 ), .Iin19 (Id_dr_y_out19 ), .Iin20 (Id_dr_y_out20 ), .Iin21 (Id_dr_y_out21 ), .Iin22 (Id_dr_y_out22 ), .Iin23 (Id_dr_y_out23 ), .Iin24 (Id_dr_y_out24 ), .Iin25 (Id_dr_y_out25 ), .Iin26 (Id_dr_y_out26 ), .Iin27 (Id_dr_y_out27 ), .Iin28 (Id_dr_y_out28 ), .Iin29 (Id_dr_y_out29 ), .Iin30 (Id_dr_y_out30 ), .Iin31 (Id_dr_y_out31 ), .Iin32 (Id_dr_y_out32 ), .Iin33 (Id_dr_y_out33 ), .Iin34 (Id_dr_y_out34 ), .Iin35 (Id_dr_y_out35 ), .Iin36 (Id_dr_y_out36 ), .Iin37 (Id_dr_y_out37 ), .Iin38 (Id_dr_y_out38 ), .Iin39 (Id_dr_y_out39 ), .Iin40 (Id_dr_y_out40 ), .Iin41 (Id_dr_y_out41 ), .Iin42 (Id_dr_y_out42 ), .Iin43 (Id_dr_y_out43 ), .Iin44 (Id_dr_y_out44 ), .Iin45 (Id_dr_y_out45 ), .Iin46 (Id_dr_y_out46 ), .Iin47 (Id_dr_y_out47 ), .Iin48 (Id_dr_y_out48 ), .Iin49 (Id_dr_y_out49 ), .Iin50 (Id_dr_y_out50 ), .Iin51 (Id_dr_y_out51 ), .Iin52 (Id_dr_y_out52 ), .Iin53 (Id_dr_y_out53 ), .Iin54 (Id_dr_y_out54 ), .Iin55 (Id_dr_y_out55 ), .Iin56 (Id_dr_y_out56 ), .Iin57 (Id_dr_y_out57 ), .Iin58 (Id_dr_y_out58 ), .Iin59 (Id_dr_y_out59 ), .Iin60 (Id_dr_y_out60 ), .Iin61 (Id_dr_y_out61 ), .Iin62 (Id_dr_y_out62 ), .Iin63 (Id_dr_y_out63 ), .Iin64 (Id_dr_y_out64 ), .Iin65 (Id_dr_y_out65 ), .Iin66 (Id_dr_y_out66 ), .Iin67 (Id_dr_y_out67 ), .Iin68 (Id_dr_y_out68 ), .Iin69 (Id_dr_y_out69 ), .Iin70 (Id_dr_y_out70 ), .Iin71 (Id_dr_y_out71 ), .Iin72 (Id_dr_y_out72 ), .Iin73 (Id_dr_y_out73 ), .Iin74 (Id_dr_y_out74 ), .Iin75 (Id_dr_y_out75 ), .Iin76 (Id_dr_y_out76 ), .Iin77 (Id_dr_y_out77 ), .Iin78 (Id_dr_y_out78 ), .Iin79 (Id_dr_y_out79 ), .Iin80 (Id_dr_y_out80 ), .Iin81 (Id_dr_y_out81 ), .Iin82 (Id_dr_y_out82 ), .Iin83 (Id_dr_y_out83 ), .Iin84 (Id_dr_y_out84 ), .Iin85 (Id_dr_y_out85 ), .Iin86 (Id_dr_y_out86 ), .Iin87 (Id_dr_y_out87 ), .Iin88 (Id_dr_y_out88 ), .Iin89 (Id_dr_y_out89 ), .Iin90 (Id_dr_y_out90 ), .Iin91 (Id_dr_y_out91 ), .Iin92 (Id_dr_y_out92 ), .Iin93 (Id_dr_y_out93 ), .Iin94 (Id_dr_y_out94 ), .Iin95 (Id_dr_y_out95 ), .Iin96 (Id_dr_y_out96 ), .Iin97 (Id_dr_y_out97 ), .Iin98 (Id_dr_y_out98 ), .Iin99 (Id_dr_y_out99 ), .Iin100 (Id_dr_y_out100 ), .Iin101 (Id_dr_y_out101 ), .Iin102 (Id_dr_y_out102 ), .Iin103 (Id_dr_y_out103 ), .Iin104 (Id_dr_y_out104 ), .Iin105 (Id_dr_y_out105 ), .Iin106 (Id_dr_y_out106 ), .Iin107 (Id_dr_y_out107 ), .Iin108 (Id_dr_y_out108 ), .Iin109 (Id_dr_y_out109 ), .Iin110 (Id_dr_y_out110 ), .Iin111 (Id_dr_y_out111 ), .Iin112 (Id_dr_y_out112 ), .Iin113 (Id_dr_y_out113 ), .Iin114 (Id_dr_y_out114 ), .Iin115 (Id_dr_y_out115 ), .Iin116 (Id_dr_y_out116 ), .Iin117 (Id_dr_y_out117 ), .Iin118 (Id_dr_y_out118 ), .Iin119 (Id_dr_y_out119 ), .Iin120 (Id_dr_y_out120 ), .Iin121 (Id_dr_y_out121 ), .Iin122 (Id_dr_y_out122 ), .Iin123 (Id_dr_y_out123 ), .Iin124 (Id_dr_y_out124 ), .Iin125 (Id_dr_y_out125 ), .Iin126 (Id_dr_y_out126 ), .Iin127 (Id_dr_y_out127 ), .Iin128 (Id_dr_y_out128 ), .Iin129 (Id_dr_y_out129 ), .Iin130 (Id_dr_y_out130 ), .Iin131 (Id_dr_y_out131 ), .Iin132 (Id_dr_y_out132 ), .Iin133 (Id_dr_y_out133 ), .Iin134 (Id_dr_y_out134 ), .Iin135 (Id_dr_y_out135 ), .Iin136 (Id_dr_y_out136 ), .Iin137 (Id_dr_y_out137 ), .Iin138 (Id_dr_y_out138 ), .Iin139 (Id_dr_y_out139 ), .Iin140 (Id_dr_y_out140 ), .Iin141 (Id_dr_y_out141 ), .Iin142 (Id_dr_y_out142 ), .Iin143 (Id_dr_y_out143 ), .Iin144 (Id_dr_y_out144 ), .Iin145 (Id_dr_y_out145 ), .Iin146 (Id_dr_y_out146 ), .Iin147 (Id_dr_y_out147 ), .Iin148 (Id_dr_y_out148 ), .Iin149 (Id_dr_y_out149 ), .Iin150 (Id_dr_y_out150 ), .Iin151 (Id_dr_y_out151 ), .Iin152 (Id_dr_y_out152 ), .Iin153 (Id_dr_y_out153 ), .Iin154 (Id_dr_y_out154 ), .Iin155 (Id_dr_y_out155 ), .Iin156 (Id_dr_y_out156 ), .Iin157 (
A_2P_U_X4 Ipu0  (.p1(Ito_pu0_d_d0 ), .p2(hs_enB), .y(Ito_pu0_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu1  (.p1(Ito_pu1_d_d0 ), .p2(hs_enB), .y(Ito_pu1_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu2  (.p1(Ito_pu2_d_d0 ), .p2(hs_enB), .y(Ito_pu2_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu3  (.p1(Ito_pu3_d_d0 ), .p2(hs_enB), .y(Ito_pu3_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu4  (.p1(Ito_pu4_d_d0 ), .p2(hs_enB), .y(Ito_pu4_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu5  (.p1(Ito_pu5_d_d0 ), .p2(hs_enB), .y(Ito_pu5_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu6  (.p1(Ito_pu6_d_d0 ), .p2(hs_enB), .y(Ito_pu6_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu7  (.p1(Ito_pu7_d_d0 ), .p2(hs_enB), .y(Ito_pu7_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu8  (.p1(Ito_pu8_d_d0 ), .p2(hs_enB), .y(Ito_pu8_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu9  (.p1(Ito_pu9_d_d0 ), .p2(hs_enB), .y(Ito_pu9_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu10  (.p1(Ito_pu10_d_d0 ), .p2(hs_enB), .y(Ito_pu10_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu11  (.p1(Ito_pu11_d_d0 ), .p2(hs_enB), .y(Ito_pu11_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu12  (.p1(Ito_pu12_d_d0 ), .p2(hs_enB), .y(Ito_pu12_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu13  (.p1(Ito_pu13_d_d0 ), .p2(hs_enB), .y(Ito_pu13_a ), .vdd(vdd), .vss(vss));
A_2P_U_X4 Ipu14  (.p1(Ito_pu14_d_d0 ), .p2(hs_enB), .y(Ito_pu14_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0ortree_315_4 I_ortree  (.Iin0 (I_ortree_in0 ), .Iin1 (I_ortree_in1 ), .Iin2 (I_ortree_in2 ), .Iin3 (I_ortree_in3 ), .Iin4 (I_ortree_in4 ), .Iin5 (I_ortree_in5 ), .Iin6 (I_ortree_in6 ), .Iin7 (I_ortree_in7 ), .Iin8 (I_ortree_in8 ), .Iin9 (I_ortree_in9 ), .Iin10 (I_ortree_in10 ), .Iin11 (I_ortree_in11 ), .Iin12 (I_ortree_in12 ), .Iin13 (I_ortree_in13 ), .Iin14 (I_ortree_in14 ), .out(I_ortree_out ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf__boolarray_315_715_4 Id_dr_xX  (.Iin0 (Id_dr_x_out0 ), .Iin1 (Id_dr_x_out1 ), .Iin2 (Id_dr_x_out2 ), .Iin3 (Id_dr_x_out3 ), .Iin4 (Id_dr_x_out4 ), .Iin5 (Id_dr_x_out5 ), .Iin6 (Id_dr_x_out6 ), .Iin7 (Id_dr_x_out7 ), .Iin8 (Id_dr_x_out8 ), .Iin9 (Id_dr_x_out9 ), .Iin10 (Id_dr_x_out10 ), .Iin11 (Id_dr_x_out11 ), .Iin12 (Id_dr_x_out12 ), .Iin13 (Id_dr_x_out13 ), .Iin14 (Id_dr_x_out14 ), .Iout0 (Iout_req_x0 ), .Iout1 (Iout_req_x1 ), .Iout2 (Iout_req_x2 ), .Iout3 (Iout_req_x3 ), .Iout4 (Iout_req_x4 ), .Iout5 (Iout_req_x5 ), .Iout6 (Iout_req_x6 ), .Iout7 (Iout_req_x7 ), .Iout8 (Iout_req_x8 ), .Iout9 (Iout_req_x9 ), .Iout10 (Iout_req_x10 ), .Iout11 (Iout_req_x11 ), .Iout12 (Iout_req_x12 ), .Iout13 (Iout_req_x13 ), .Iout14 (Iout_req_x14 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0vtree_34_4 Ivtree_x  (.Iin_d0_d0 (Id_dr_x_final_refresh_d0_d0 ), .Iin_d0_d1 (Id_dr_x_final_refresh_d0_d1 ), .Iin_d1_d0 (Id_dr_x_final_refresh_d1_d0 ), .Iin_d1_d1 (Id_dr_x_final_refresh_d1_d1 ), .Iin_d2_d0 (Id_dr_x_final_refresh_d2_d0 ), .Iin_d2_d1 (Id_dr_x_final_refresh_d2_d1 ), .Iin_d3_d0 (Id_dr_x_final_refresh_d3_d0 ), .Iin_d3_d1 (Id_dr_x_final_refresh_d3_d1 ), .out(Ivtree_x_out ), .vdd(vdd), .vss(vss));
A_2C_B_X1 Ibuf_ack_Cel  (.y(Iack_mux_b ), .c1(I_ortree_out ), .c2(Iack_mux_a ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_39_7348_4 Id_dr_y  (.Iin_d0_d0 (Id_dr_y_in_d0_d0 ), .Iin_d0_d1 (Id_dr_y_in_d0_d1 ), .Iin_d1_d0 (Id_dr_y_in_d1_d0 ), .Iin_d1_d1 (Id_dr_y_in_d1_d1 ), .Iin_d2_d0 (Id_dr_y_in_d2_d0 ), .Iin_d2_d1 (Id_dr_y_in_d2_d1 ), .Iin_d3_d0 (Id_dr_y_in_d3_d0 ), .Iin_d3_d1 (Id_dr_y_in_d3_d1 ), .Iin_d4_d0 (Id_dr_y_in_d4_d0 ), .Iin_d4_d1 (Id_dr_y_in_d4_d1 ), .Iin_d5_d0 (Id_dr_y_in_d5_d0 ), .Iin_d5_d1 (Id_dr_y_in_d5_d1 ), .Iin_d6_d0 (Id_dr_y_in_d6_d0 ), .Iin_d6_d1 (Id_dr_y_in_d6_d1 ), .Iin_d7_d0 (Id_dr_y_in_d7_d0 ), .Iin_d7_d1 (Id_dr_y_in_d7_d1 ), .Iin_d8_d0 (Id_dr_y_in_d8_d0 ), .Iin_d8_d1 (Id_dr_y_in_d8_d1 ), .Iout0 (Id_dr_y_out0 ), .Iout1 (Id_dr_y_out1 ), .Iout2 (Id_dr_y_out2 ), .Iout3 (Id_dr_y_out3 ), .Iout4 (Id_dr_y_out4 ), .Iout5 (Id_dr_y_out5 ), .Iout6 (Id_dr_y_out6 ), .Iout7 (Id_dr_y_out7 ), .Iout8 (Id_dr_y_out8 ), .Iout9 (Id_dr_y_out9 ), .Iout10 (Id_dr_y_out10 ), .Iout11 (Id_dr_y_out11 ), .Iout12 (Id_dr_y_out12 ), .Iout13 (Id_dr_y_out13 ), .Iout14 (Id_dr_y_out14 ), .Iout15 (Id_dr_y_out15 ), .Iout16 (Id_dr_y_out16 ), .Iout17 (Id_dr_y_out17 ), .Iout18 (Id_dr_y_out18 ), .Iout19 (Id_dr_y_out19 ), .Iout20 (Id_dr_y_out20 ), .Iout21 (Id_dr_y_out21 ), .Iout22 (Id_dr_y_out22 ), .Iout23 (Id_dr_y_out23 ), .Iout24 (Id_dr_y_out24 ), .Iout25 (Id_dr_y_out25 ), .Iout26 (Id_dr_y_out26 ), .Iout27 (Id_dr_y_out27 ), .Iout28 (Id_dr_y_out28 ), .Iout29 (Id_dr_y_out29 ), .Iout30 (Id_dr_y_out30 ), .Iout31 (Id_dr_y_out31 ), .Iout32 (Id_dr_y_out32 ), .Iout33 (Id_dr_y_out33 ), .Iout34 (Id_dr_y_out34 ), .Iout35 (Id_dr_y_out35 ), .Iout36 (Id_dr_y_out36 ), .Iout37 (Id_dr_y_out37 ), .Iout38 (Id_dr_y_out38 ), .Iout39 (Id_dr_y_out39 ), .Iout40 (Id_dr_y_out40 ), .Iout41 (Id_dr_y_out41 ), .Iout42 (Id_dr_y_out42 ), .Iout43 (Id_dr_y_out43 ), .Iout44 (Id_dr_y_out44 ), .Iout45 (Id_dr_y_out45 ), .Iout46 (Id_dr_y_out46 ), .Iout47 (Id_dr_y_out47 ), .Iout48 (Id_dr_y_out48 ), .Iout49 (Id_dr_y_out49 ), .Iout50 (Id_dr_y_out50 ), .Iout51 (Id_dr_y_out51 ), .Iout52 (Id_dr_y_out52 ), .Iout53 (Id_dr_y_out53 ), .Iout54 (Id_dr_y_out54 ), .Iout55 (Id_dr_y_out55 ), .Iout56 (Id_dr_y_out56 ), .Iout57 (Id_dr_y_out57 ), .Iout58 (Id_dr_y_out58 ), .Iout59 (Id_dr_y_out59 ), .Iout60 (Id_dr_y_out60 ), .Iout61 (Id_dr_y_out61 ), .Iout62 (Id_dr_y_out62 ), .Iout63 (Id_dr_y_out63 ), .Iout64 (Id_dr_y_out64 ), .Iout65 (Id_dr_y_out65 ), .Iout66 (Id_dr_y_out66 ), .Iout67 (Id_dr_y_out67 ), .Iout68 (Id_dr_y_out68 ), .Iout69 (Id_dr_y_out69 ), .Iout70 (Id_dr_y_out70 ), .Iout71 (Id_dr_y_out71 ), .Iout72 (Id_dr_y_out72 ), .Iout73 (Id_dr_y_out73 ), .Iout74 (Id_dr_y_out74 ), .Iout75 (Id_dr_y_out75 ), .Iout76 (Id_dr_y_out76 ), .Iout77 (Id_dr_y_out77 ), .Iout78 (Id_dr_y_out78 ), .Iout79 (Id_dr_y_out79 ), .Iout80 (Id_dr_y_out80 ), .Iout81 (Id_dr_y_out81 ), .Iout82 (Id_dr_y_out82 ), .Iout83 (Id_dr_y_out83 ), .Iout84 (Id_dr_y_out84 ), .Iout85 (Id_dr_y_out85 ), .Iout86 (Id_dr_y_out86 ), .Iout87 (Id_dr_y_out87 ), .Iout88 (Id_dr_y_out88 ), .Iout89 (Id_dr_y_out89 ), .Iout90 (Id_dr_y_out90 ), .Iout91 (Id_dr_y_out91 ), .Iout92 (Id_dr_y_out92 ), .Iout93 (Id_dr_y_out93 ), .Iout94 (Id_dr_y_out94 ), .Iout95 (Id_dr_y_out95 ), .Iout96 (Id_dr_y_out96 ), .Iout97 (Id_dr_y_out97 ), .Iout98 (Id_dr_y_out98 ), .Iout99 (Id_dr_y_out99 ), .Iout100 (Id_dr_y_out100 ), .Iout101 (Id_dr_y_out101 ), .Iout102 (Id_dr_y_out102 ), .Iout103 (Id_dr_y_out103 ), .Iout104 (Id_dr_y_out104 ), .Iout105 (Id_dr_y_out105 ), .Iout106 (Id_dr_y_out106 ), .Iout107 (Id_dr_y_out107 ), .Iout108 (Id_dr_y_out108 ), .Iout109 (Id_dr_y_out109 ), .Iout110 (Id_dr_y_out110 ), .Iout111 (Id_dr_y_out111 ), .Iout112 (Id_dr_y_out112 ), .Iout113 (Id_dr_y_out113 ), .Iout114 (Id_dr_y_out114 ), .Iout115 (Id_dr_y_out115 ), .Iout116 (Id_dr_y_out116 ), .Iout117 (Id_dr_y_out117 ), .Iout118 (Id_dr_y_out118 ), .Iout119 (Id_dr_y_out119 ), .Iout120 (Id_dr_y_out120 ), .Iout121 (Id_dr_y_out121 ), .Iout122 (Id_dr_y_out122 ), .Iout123 (Id_dr_y_out123 ), .Iout124 (Id_dr_y_out124 ), .Iout125 (Id_dr_y_out125 ), .Iout126 (Id_dr_y_out126 ), .Iout127 (Id_dr_y_out127 ), .Iout128 (Id_dr_y_out128 ), .Iout129 (Id_dr_y_out129 ), .Iout130 (Id_dr_y_out130 
INV_X1 Iack_disableB  (.y(Iack_block_b ), .a(ack_disable), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0buffer_313_4 Iaddr_buf  (.Iin_d_d0_d0 (Iin_d_d0_d0 ), .Iin_d_d0_d1 (Iin_d_d0_d1 ), .Iin_d_d1_d0 (Iin_d_d1_d0 ), .Iin_d_d1_d1 (Iin_d_d1_d1 ), .Iin_d_d2_d0 (Iin_d_d2_d0 ), .Iin_d_d2_d1 (Iin_d_d2_d1 ), .Iin_d_d3_d0 (Iin_d_d3_d0 ), .Iin_d_d3_d1 (Iin_d_d3_d1 ), .Iin_d_d4_d0 (Iin_d_d4_d0 ), .Iin_d_d4_d1 (Iin_d_d4_d1 ), .Iin_d_d5_d0 (Iin_d_d5_d0 ), .Iin_d_d5_d1 (Iin_d_d5_d1 ), .Iin_d_d6_d0 (Iin_d_d6_d0 ), .Iin_d_d6_d1 (Iin_d_d6_d1 ), .Iin_d_d7_d0 (Iin_d_d7_d0 ), .Iin_d_d7_d1 (Iin_d_d7_d1 ), .Iin_d_d8_d0 (Iin_d_d8_d0 ), .Iin_d_d8_d1 (Iin_d_d8_d1 ), .Iin_d_d9_d0 (Iin_d_d9_d0 ), .Iin_d_d9_d1 (Iin_d_d9_d1 ), .Iin_d_d10_d0 (Iin_d_d10_d0 ), .Iin_d_d10_d1 (Iin_d_d10_d1 ), .Iin_d_d11_d0 (Iin_d_d11_d0 ), .Iin_d_d11_d1 (Iin_d_d11_d1 ), .Iin_d_d12_d0 (Iin_d_d12_d0 ), .Iin_d_d12_d1 (Iin_d_d12_d1 ), .Iin_a (Iin_a ), .Iin_v (Iin_v ), .Iout_d_d0_d0 (Id_dr_x_in_d0_d0 ), .Iout_d_d0_d1 (Id_dr_x_in_d0_d1 ), .Iout_d_d1_d0 (Id_dr_x_in_d1_d0 ), .Iout_d_d1_d1 (Id_dr_x_in_d1_d1 ), .Iout_d_d2_d0 (Id_dr_x_in_d2_d0 ), .Iout_d_d2_d1 (Id_dr_x_in_d2_d1 ), .Iout_d_d3_d0 (Id_dr_x_in_d3_d0 ), .Iout_d_d3_d1 (Id_dr_x_in_d3_d1 ), .Iout_d_d4_d0 (Id_dr_y_in_d0_d0 ), .Iout_d_d4_d1 (Id_dr_y_in_d0_d1 ), .Iout_d_d5_d0 (Id_dr_y_in_d1_d0 ), .Iout_d_d5_d1 (Id_dr_y_in_d1_d1 ), .Iout_d_d6_d0 (Id_dr_y_in_d2_d0 ), .Iout_d_d6_d1 (Id_dr_y_in_d2_d1 ), .Iout_d_d7_d0 (Id_dr_y_in_d3_d0 ), .Iout_d_d7_d1 (Id_dr_y_in_d3_d1 ), .Iout_d_d8_d0 (Id_dr_y_in_d4_d0 ), .Iout_d_d8_d1 (Id_dr_y_in_d4_d1 ), .Iout_d_d9_d0 (Id_dr_y_in_d5_d0 ), .Iout_d_d9_d1 (Id_dr_y_in_d5_d1 ), .Iout_d_d10_d0 (Id_dr_y_in_d6_d0 ), .Iout_d_d10_d1 (Id_dr_y_in_d6_d1 ), .Iout_d_d11_d0 (Id_dr_y_in_d7_d0 ), .Iout_d_d11_d1 (Id_dr_y_in_d7_d1 ), .Iout_d_d12_d0 (Id_dr_y_in_d8_d0 ), .Iout_d_d12_d1 (Id_dr_y_in_d8_d1 ), .Iout_a (Iack_block_y ), .Iout_v (Iack_mux_a ), .reset_B(reset_B), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset0  (.p1(I_reset_BX0 ), .y(Ito_pu0_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset1  (.p1(I_reset_BX0 ), .y(Ito_pu1_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset2  (.p1(I_reset_BX0 ), .y(Ito_pu2_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset3  (.p1(I_reset_BX0 ), .y(Ito_pu3_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset4  (.p1(I_reset_BX0 ), .y(Ito_pu4_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset5  (.p1(I_reset_BX0 ), .y(Ito_pu5_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset6  (.p1(I_reset_BX0 ), .y(Ito_pu6_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset7  (.p1(I_reset_BX0 ), .y(Ito_pu7_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset8  (.p1(I_reset_BX0 ), .y(Ito_pu8_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset9  (.p1(I_reset_BX0 ), .y(Ito_pu9_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset10  (.p1(I_reset_BX0 ), .y(Ito_pu10_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset11  (.p1(I_reset_BX0 ), .y(Ito_pu11_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset12  (.p1(I_reset_BX0 ), .y(Ito_pu12_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset13  (.p1(I_reset_BX0 ), .y(Ito_pu13_a ), .vdd(vdd), .vss(vss));
A_1P_U_X4 Ipu_reset14  (.p1(I_reset_BX0 ), .y(Ito_pu14_a ), .vdd(vdd), .vss(vss));
endmodule