actlib_dataflow_neuro/test/unit_tests/texel_dualcore_glue/split_modules/tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4/netlist/verilog.v

module tmpl_0_0dataflow__neuro_0_0decoder__dualrail__en_35_730_4(Iin_d0_d0 , Iin_d0_d1 , Iin_d1_d0 , Iin_d1_d1 , Iin_d2_d0 , Iin_d2_d1 , Iin_d3_d0 , Iin_d3_d1 , Iin_d4_d0 , Iin_d4_d1 , en, Iout0 , Iout1 , Iout2 , Iout3 , Iout4 , Iout5 , Iout6 , Iout7 , Iout8 , Iout9 , Iout10 , Iout11 , Iout12 , Iout13 , Iout14 , Iout15 , Iout16 , Iout17 , Iout18 , Iout19 , Iout20 , Iout21 , Iout22 , Iout23 , Iout24 , Iout25 , Iout26 , Iout27 , Iout28 , Iout29 , vdd, vss); 
   input vdd;
   input vss;
   input Iin_d0_d0 ;
   input Iin_d0_d1 ;
   input Iin_d1_d0 ;
   input Iin_d1_d1 ;
   input Iin_d2_d0 ;
   input Iin_d2_d1 ;
   input Iin_d3_d0 ;
   input Iin_d3_d1 ;
   input Iin_d4_d0 ;
   input Iin_d4_d1 ;
   input en;
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   

// -- signals ---
   wire Idecoder_final_refresh_d4_d1 ;
   output Iout22 ;
   wire Iin_d0_d0 ;
   wire Idecoder_final_refresh_d3_d0 ;
   wire Idecoder_final_refresh_d2_d0 ;
   output Iout29 ;
   output Iout7 ;
   output Iout4 ;
   wire Iin_d0_d1 ;
   wire Ien_ands_t4_y ;
   wire Ien_ands_t2_y ;
   wire Iin_d4_d0 ;
   wire Idecoder_final_refresh_d0_d1 ;
   wire Idecoder_final_refresh_d1_d0 ;
   output Iout26 ;
   output Iout0 ;
   wire Iin_d3_d0 ;
   output Iout13 ;
   output Iout17 ;
   output Iout10 ;
   wire Iin_d3_d1 ;
   output Iout15 ;
   output Iout5 ;
   output Iout24 ;
   wire Ien_ands_f2_y ;
   wire Idecoder_final_refresh_d1_d1 ;
   output Iout20 ;
   output Iout18 ;
   output Iout16 ;
   output Iout3 ;
   output Iout2 ;
   output Iout8 ;
   wire Ien_ands_f1_y ;
   wire Iin_d1_d1 ;
   output Iout21 ;
   wire Ien_ands_t3_y ;
   wire en;
   output Iout6 ;
   output Iout1 ;
   output Iout19 ;
   output Iout9 ;
   wire Iin_d4_d1 ;
   wire Idecoder_final_refresh_d3_d1 ;
   wire Idecoder_final_refresh_d2_d1 ;
   wire Ien_ands_f4_y ;
   wire Ien_ands_f3_y ;
   output Iout12 ;
   wire Idecoder_final_refresh_d4_d0 ;
   wire Ien_ands_t1_y ;
   output Iout14 ;
   wire Iin_d2_d1 ;
   output Iout27 ;
   wire Ien_ands_f0_y ;
   wire Iin_d1_d0 ;
   output Iout28 ;
   output Iout25 ;
   wire Ien_ands_t0_y ;
   wire Iin_d2_d0 ;
   wire Isb_en_out0 ;
   wire Idecoder_final_refresh_d0_d0 ;
   output Iout23 ;
   output Iout11 ;

// --- instances
tmpl_0_0dataflow__neuro_0_0decoder__dualrail__refresh_35_730_4 Idecoder  (.Iin_d0_d0 (Ien_ands_f0_y ), .Iin_d0_d1 (Ien_ands_t0_y ), .Iin_d1_d0 (Ien_ands_f1_y ), .Iin_d1_d1 (Ien_ands_t1_y ), .Iin_d2_d0 (Ien_ands_f2_y ), .Iin_d2_d1 (Ien_ands_t2_y ), .Iin_d3_d0 (Ien_ands_f3_y ), .Iin_d3_d1 (Ien_ands_t3_y ), .Iin_d4_d0 (Ien_ands_f4_y ), .Iin_d4_d1 (Ien_ands_t4_y ), .Iout0 (Iout0 ), .Iout1 (Iout1 ), .Iout2 (Iout2 ), .Iout3 (Iout3 ), .Iout4 (Iout4 ), .Iout5 (Iout5 ), .Iout6 (Iout6 ), .Iout7 (Iout7 ), .Iout8 (Iout8 ), .Iout9 (Iout9 ), .Iout10 (Iout10 ), .Iout11 (Iout11 ), .Iout12 (Iout12 ), .Iout13 (Iout13 ), .Iout14 (Iout14 ), .Iout15 (Iout15 ), .Iout16 (Iout16 ), .Iout17 (Iout17 ), .Iout18 (Iout18 ), .Iout19 (Iout19 ), .Iout20 (Iout20 ), .Iout21 (Iout21 ), .Iout22 (Iout22 ), .Iout23 (Iout23 ), .Iout24 (Iout24 ), .Iout25 (Iout25 ), .Iout26 (Iout26 ), .Iout27 (Iout27 ), .Iout28 (Iout28 ), .Iout29 (Iout29 ), .Ifinal_refresh_d0_d0 (Idecoder_final_refresh_d0_d0 ), .Ifinal_refresh_d0_d1 (Idecoder_final_refresh_d0_d1 ), .Ifinal_refresh_d1_d0 (Idecoder_final_refresh_d1_d0 ), .Ifinal_refresh_d1_d1 (Idecoder_final_refresh_d1_d1 ), .Ifinal_refresh_d2_d0 (Idecoder_final_refresh_d2_d0 ), .Ifinal_refresh_d2_d1 (Idecoder_final_refresh_d2_d1 ), .Ifinal_refresh_d3_d0 (Idecoder_final_refresh_d3_d0 ), .Ifinal_refresh_d3_d1 (Idecoder_final_refresh_d3_d1 ), .Ifinal_refresh_d4_d0 (Idecoder_final_refresh_d4_d0 ), .Ifinal_refresh_d4_d1 (Idecoder_final_refresh_d4_d1 ), .vdd(vdd), .vss(vss));
tmpl_0_0dataflow__neuro_0_0sigbuf_310_4 Isb_en  (.in(en), .Iout0 (Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t0  (.y(Ien_ands_t0_y ), .a(Iin_d0_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t1  (.y(Ien_ands_t1_y ), .a(Iin_d1_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t2  (.y(Ien_ands_t2_y ), .a(Iin_d2_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t3  (.y(Ien_ands_t3_y ), .a(Iin_d3_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_t4  (.y(Ien_ands_t4_y ), .a(Iin_d4_d1 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f0  (.y(Ien_ands_f0_y ), .a(Iin_d0_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f1  (.y(Ien_ands_f1_y ), .a(Iin_d1_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f2  (.y(Ien_ands_f2_y ), .a(Iin_d2_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f3  (.y(Ien_ands_f3_y ), .a(Iin_d3_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
AND2_X1 Ien_ands_f4  (.y(Ien_ands_f4_y ), .a(Iin_d4_d0 ), .b(Isb_en_out0 ), .vdd(vdd), .vss(vss));
endmodule