continued register_rw

test/unit_tests/register_wrw/test.prsim

@@ -3,6 +3,7 @@ system "echo '[0] start test'"
 system "echo '----------------------------------------------------------'"
 
 set-qdi-channel-neutral "t.in" 5
+set-qdi-channel-neutral "t.out" 4
 set t.data[0].d[0] 0
 set t.data[0].d[1] 0
 set t.data[1].d[0] 0
@@ -11,9 +12,15 @@ set t.dly_cfg[0] 1
 set t.dly_cfg[1] 1
 set t.out.a 0
 set t.out.v 0
+cycle
 #set t.registers._in_write.a 0
 set Reset 0
+set t.dly_cfg[0] 1
+set t.dly_cfg[1] 1
 cycle
+assert-qdi-channel-neutral "t.in" 5
+assert-qdi-channel-neutral "t.out" 4
+# There shouldnt be any status X
 status X
 #mode run
 cycle
@@ -45,21 +52,29 @@ assert t.registers.ff[0].q 1
 assert t.registers.ff[1].q 1
 assert t.registers.ff[2].q 0
 assert t.registers.ff[3].q 0
+assert t.registers.ff[4].q 0
+assert t.registers.ff[5].q 0
+assert t.registers.ff[6].q 0
+assert t.registers.ff[7].q 0
 
 system "echo '[3] first writing done'"
 system "echo '----------------------------------------------------------'"
 
 set-qdi-channel-valid "t.in" 5 16
-# 16 -> 10000 -> reading mode, address 00, word 00 (word doesn't needed here)
+# 16 -> 10000 -> reading mode, address 00, word 00 (word doesnt needed here)
 cycle
+assert t.registers._clock_temp_inv 1
 assert-qdi-channel-valid "t.out" 4 3
 set t.out.v 1
 cycle
 set t.out.a 1
+assert t.registers._clock_temp_inv 1
 cycle
 assert t.in.a 1
 set-qdi-channel-neutral "t.in" 5
+assert t.registers._clock_temp_inv 1
 cycle
+assert t.registers._clock_temp_inv 1
 assert t.registers.ff[0].q 1
 assert t.registers.ff[1].q 1
 assert t.registers.ff[2].q 0