we have liftoff - lisp code still needs fixing

ctree/ortree/sigbuf all tests working
This commit is contained in:
2022-02-22 11:25:55 +01:00
parent 90a429181e
commit 0772df30a5
12 changed files with 98 additions and 26 deletions

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t.sigbuf_test.buf6._y t.in t.out
0
1

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= "GND" "GND"
= "Vdd" "Vdd"
"t.sigbuf_test.buf6.a"->"t.sigbuf_test.buf6._y"-
~("t.sigbuf_test.buf6.a")->"t.sigbuf_test.buf6._y"+
"t.sigbuf_test.buf6._y"->"t.sigbuf_test.buf6.y"-
~("t.sigbuf_test.buf6._y")->"t.sigbuf_test.buf6.y"+
= "t.sigbuf_test.supply.vdd" "t.sigbuf_test.buf6.vdd"
= "t.sigbuf_test.supply.vss" "t.sigbuf_test.buf6.vss"
= "t.sigbuf_test.out" "t.sigbuf_test.buf6.y"
= "t.sigbuf_test.in" "t.sigbuf_test.buf6.a"
= "Vdd" "t.sigbuf_test.supply.vdd"
= "GND" "t.sigbuf_test.supply.vss"
= "t.out" "t.sigbuf_test.out"
= "t.in" "t.sigbuf_test.in"

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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
//import "../../dataflow_neuro/treegates.act";
//open tmpl::dataflow_neuro;
//sigbuf<3> buff_test;
import "../../dataflow_neuro/treegates.act";
import globals;
open tmpl::dataflow_neuro;
defproc sigbuf_15 (bool? in; bool! out){
sigbuf<15> sigbuf_test(.in=in, .out=out);
sigbuf_test.supply.vss = GND;
sigbuf_test.supply.vdd = Vdd;
}
sigbuf_15 t;

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system "echo '0'"
set t.in 0
system "echo '1'"
cycle
mode run
assert t.out 0