we have liftoff - lisp code still needs fixing
ctree/ortree/sigbuf all tests working
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3
test/unit_tests/sigbuf_15/run/prsim.out
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3
test/unit_tests/sigbuf_15/run/prsim.out
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t.sigbuf_test.buf6._y t.in t.out
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0
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1
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14
test/unit_tests/sigbuf_15/run/test.prs
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14
test/unit_tests/sigbuf_15/run/test.prs
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= "GND" "GND"
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= "Vdd" "Vdd"
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"t.sigbuf_test.buf6.a"->"t.sigbuf_test.buf6._y"-
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~("t.sigbuf_test.buf6.a")->"t.sigbuf_test.buf6._y"+
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"t.sigbuf_test.buf6._y"->"t.sigbuf_test.buf6.y"-
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~("t.sigbuf_test.buf6._y")->"t.sigbuf_test.buf6.y"+
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= "t.sigbuf_test.supply.vdd" "t.sigbuf_test.buf6.vdd"
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= "t.sigbuf_test.supply.vss" "t.sigbuf_test.buf6.vss"
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= "t.sigbuf_test.out" "t.sigbuf_test.buf6.y"
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= "t.sigbuf_test.in" "t.sigbuf_test.buf6.a"
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= "Vdd" "t.sigbuf_test.supply.vdd"
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= "GND" "t.sigbuf_test.supply.vss"
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= "t.out" "t.sigbuf_test.out"
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= "t.in" "t.sigbuf_test.in"
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48
test/unit_tests/sigbuf_15/test.act
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48
test/unit_tests/sigbuf_15/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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//import "../../dataflow_neuro/treegates.act";
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//open tmpl::dataflow_neuro;
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//sigbuf<3> buff_test;
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import "../../dataflow_neuro/treegates.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc sigbuf_15 (bool? in; bool! out){
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sigbuf<15> sigbuf_test(.in=in, .out=out);
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sigbuf_test.supply.vss = GND;
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sigbuf_test.supply.vdd = Vdd;
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}
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sigbuf_15 t;
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12
test/unit_tests/sigbuf_15/test.prsim
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12
test/unit_tests/sigbuf_15/test.prsim
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system "echo '0'"
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set t.in 0
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system "echo '1'"
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cycle
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mode run
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assert t.out 0
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