regenned texel dualcore innovus fairly finaly??

dataflow_neuro/chips.act

@@ -271,7 +271,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
         sb_nrn_EFO.in[i] = register.data[5].d[i].t;
     )
 
-    // Create buffered signals from register to synapses.
+    // Create  buffered signals from register to synapses.
     // Includes safety on the first 3 flags with dev mon.
     sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
     (i:3..N_FLAGS_PER_SYN-1:
@@ -281,7 +281,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
     (i:0..2:
         syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
         syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
-        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y
+        sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
 
         syn_flags_dev_safety[i].vdd = supply.vdd;
         syn_flags_dev_safety[i].vss = supply.vss;
@@ -412,6 +412,9 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
+
     Mx1of2<REG_NCW> c2_reg_data[REG_M];
 
     bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
@@ -427,16 +430,13 @@ defproc texel_dualcore (bd<N_IN> in, out;
     bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+    
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
     power supply;
-    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
-    
-    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
-    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
-
-    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
-    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X]
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
     ){
 
     // Reset buffers

test/unit_tests/texel_dualcore_innovus/run/prsim.out

@@ -1 +1 @@
-c.c.core2.register.registers[1].buf.en_buf.out[0] c.c1_reg_data[21].d[4].t c.c2_dec_req_y[295] c.c.core2.decoder.d_dr_y.in_tX[5].y c.c.core2.syn_mon_y_buf.in[97] c.c.core2.register.out_ortrees_t[0].tmp[64] c.c.core2.register.registers[12].gandalf_t[20].y c.c.core1.register.and_reads_t[583].y c.c.core1.syn_mon_dec_y.decoder.in_fX[17].y c.c.core2.decoder.d_dr_y.in_fX[17].y c.c.core1.decoder.d_dr_y.atree[299].tmp[10] c.c.core1.append_enc.sb.out[0] c.c1_reg_data[56].d[22].f c.c.core1.fifo_out.fifo_element[2]._reset_BXX[0] c.c1_syn_mon_y[346] c.c.core2.register.read_selectorsX.sb[21].buf12._y c.c.core2.register.registers[25].out_valid.ct.in[4] c.c1_reg_data[60].d[1].t c.c.core1._demux.demux.demux.out_en_buf.out[0] c.c1_reg_data[60].d[20].f c.c.core2.fifo_dmx2dec.fifo_element[0]._out_a_BX[0] c.c.core2.syn_mon_dec_y.decoder.in_tX[4].y c.c.core1.register.registers[26].gandalf_f[16].y c.c1_dec_req_y[293] c.c2_dec_req_y[121] c.c.core2.register.and_reads_f[1353].y c.c2_reg_data[62].d[15].t c.c.core1.register.registers[28].buf._resetX[0] c.c.core1.register.registers[3].buf._resetX[0] c.c.core2.register.input_valid.OR2_tf[18].b c.c.fifo_drop2mrg.fifo_element[1].vc.ct.in[22] c.c.core1.syn_mon_y_buf.in[295] c.c2_dec_req_y[10] c.c.core2.decoder.d_dr_y.atree[335].tmp[13] c.c2_syn_mon_y[107] c.c.core2.register.registers[31].buf.en_buf.out[0] c.c.core2.register.registers[21].passX.out[0] c.c2_reg_data[1].d[5].t c.c.core1.register.out_ortrees_t[19].tmp[75] c.c.core2.register.registers[36].buf._resetX[0] c.c1_reg_data[49].d[4].f c.c.fifo_dmx2core1.fifo_element[1].vc.OR2_tf[9]._y c.c1_dec_req_y[8] c.c.core1.register.out_ortrees_f[10].tmp[115] c.c.core1.register.and_reads_f[1354].y c.c.core1.register.and_reads_f[93].y c.c2_dec_req_y[197] c.c2_syn_mon_y[310] c.c2_syn_mon_y[179] c.c.core2.syn_mon_dec_y.decoder.atree[103].tmp[14] c.c.fifo_fork2drop.fifo_element[0].t_buf_func[15].y c.c1_reg_data[36].d[13].f c.c2_reg_data[54].d[16].f c.c.core1.register.and_reads_t[405].y c.c.core1.decoder.d_dr_y.atree[324].and2s[4]._y c.c.core1.register.registers[36].buf.en_buf.out[0] c.c1_reg_data[1].d[9].f c.c.core1.register.registers[44].out_valid.OR2_tf[15]._y c.c1_syn_mon_y[236] c.c.core2.decoder.d_dr_y.in_fX[23].y c.c2_reg_data[22].d[6].f c.c1_reg_data[27].d[0].f c.c.fifo_dmx2core2.fifo_element[1].f_buf_func[16].y c.c.core2.register.registers[23].out_valid.ct.tmp[26] c.c.core1.register.registers[35].out_valid.OR2_tf[18]._y c.c.fifo_dmx2core1.fifo_element[2].in.a c.c1_reg_data[20].d[3].t c.c.core1.fifo_reg2mrg.fifo_element[2]._reset_BXX[0] c.c.core2.syn_mon_dec_y.decoder.atree[184].tmp[9] c.c1_syn_mon_y[254] c.c.core2.syn_mon_y_buf.in[150] c.c2_syn_mon_y[9] c.c.core1.register.registers[13].buf.vc.ct.C2Els[15]._y c.c.core1.decoder.d_dr_y.atree[94].tmp[12] c.c.core1.register.registers[58].buf.en_buf.out[0] c.c.core2.decoder.dly.dly[11].bufchain[8].y c.c.core2.decoder.d_dr_y.in_tX[27].y c.c.core2.fifo_dmx2reg.fifo_element[1].vc.ct.in[5] c.c.core2.register.registers[31].buf._resetX[0] c.c2_dec_req_y[93] c.c.core2.register.and_reads_t[1241].y c.c2_reg_data[37].d[7].f c.c.fifo_fork2drop.fifo_element[1].f_buf_func[5].y c.c.core1.register.registers[41].gandalf_f[3].y c.c.core2.register.and_reads_f[1012].b c.c.fifo_dmx2core2.fifo_element[0].t_buf_func[14].n1 c.c.core1.decoder.d_dr_y.out[285] c.c.core2.register.registers[7].buf.vc.ct.C2Els[13]._y c.c.fifo_drop2mrg.fifo_element[1].f_buf_func[21].y c.c1_dec_req_y[186] c.c.core2.merge_enc8reg.merge_func_f[0].na2 c.c._qdi2bd.buf.t_buf_func[14].n1 c.c.core1.register.out_ortrees_f[2].tmp[89] c.c.core2.syn_mon_dec_y.decoder.atree[96].and2s[5]._y c.c.core1.decoder.d_dr_y.atree[223].tmp[14] c.c.core1.fifo_in.fifo_element[2].en_buf.out[0] c.c.core2.syn_mon_dec_y.decoder.atree[186].and3s[0]._y c.c1_reg_data[13].d[10].f c.c1_reg_data[57].d[17].f c.c.core1.syn_mon_dec_y.decoder.atree[305].tmp[11] c.c.core2.fifo_enc2mrg.fifo_element[1].in.v c.c.core2.register.registers[18].gandalf_f[2]._y c.c1_reg_data[1].d[11].f c.c.fifo_drop2mrg.fifo_element[1].t_buf_func[6].y c.c.core1.register.registers[63].passX.out[0] c.c.core1.register.input_valid.OR2_tf[28].a c.c.core1.decoder.d_dr_y.atree[83].and2s[4]._y c.c2_reg_data[39].d[8].f c.c1_dec_req_y[234] c.c.fifo_fork2dmx.fifo_element[2]._out_a_BX[0] c.c2_reg_data[18].d[9].t c.reset_reg_B c.c.core1.syn_mon_dec_y.decoder.in_tX[9].y c.c2_reg_data[4].d[16].t c.c.core2.syn_mon_dec_y.decoder.in_tX[21].y c.c.core1.register.registers[26].buf._flushBX[0] c.c.core1.register.registers[0].gandalf_t[18].y c.c.core1.register.registers[60].passX.out[0] c.c.core1.register.registers[59]._out_v c.c.core2.register.and_reads_f[897].b c.c.core1.register.registers[37].gandalf_f[8].y c.c.core1.register.registers[31].gandalf_f[17].y c.c.core1.decoder.d_dr_y.atree[117].and2s[2]._y c.c.core2.register.and_reads_t[169].y c.c.core2.fifo_dmx2reg.fifo_element[2]._reset_BXX[0] c.c.core2.register.registers[58].buf._resetX[0] c.c1_syn_mon_x[25] c.c.core1.register.registers[18].buf._resetX[0] c.c.core1.decoder.d_dr_Line truncated
+c.c1_reg_data[10].d[13].t c.c.c.core1.register.registers[45].gandalf_t[10].y c.c.c.core2.register.and_reads_f[874].b c.c.c.fifo_fork2dmx.fifo_element[1].en_buf.out[0] c.c.c.core1.register.decoder.atree[0].in[2] c.c.c._qdi2bd.dly.dly[9].bufchain[11].y c.c.c.core1.register.out_ortrees_f[6].tmp[112] c.c2_dec_req_y[194] c.c.c.core2.register.out_ortrees_f[22].tmp[90] c.c1_dec_req_y[21] c.c.c.fifo_core2out.fifo_element[0].f_buf_func[6].y c.c.c.core2.fifo_reg2mrg.fifo_element[0].vc.ct.in[13] c.c.c.core2.register.registers[5].gandalf_t[0].y c.c1_dec_req_y[51] c.c.c.core1.syn_mon_dec_y.decoder.in_fX[25].y c.c.c.core2.register.registers[48].out_valid.ct.tmp[30] c.c.c.core2.register.registers[14].passX.out[0] c.c.c.fifo_fork2dmx.fifo_element[2].en_buf.out[0] c.c.c.core2.register.registers[8].passX.out[0] c.c1_dec_req_y[269] c.c.c.core1.register.registers[63].out_valid.ct.tmp[38] c.c.c.core2.decoder.d_dr_y.out[319] c.c.c.core1.decoder.d_dr_y.in_fX[3].y c.c.c.core1.decoder.d_dr_y.atree[218].tmp[12] c.c.c.core2.register.registers[27].out_valid.ct.in[0] c.c2_reg_data[60].d[16].t c.c1_reg_data[26].d[11].t c.c.c.core2.merge_enc8reg.vc1.ct.in[10] c.c2_reg_data[44].d[0].f c.c.c.core2.register.registers[2].buf._flushBX[0] c.c.c.core1.register.registers[24]._flush c.c.c.merge_core1x2.merge_func_t[3].na2 c.c2_reg_data[44].d[2].t c.c.c.core1.register.registers[18].buf._reset_BX[0] c.c.c.core1.register.and_reads_t[574].y c.c.c.core1.decoder.d_dr_y.atree[294].tmp[14] c.c.c.core1.register.and_reads_f[879].y c.c1_reg_data[36].d[13].f c.c.c.core2.decoder.d_dr_y.out[138] c.c.c.core2.register.registers[22].gandalf_t[4].y c.c2_reg_data[35].d[4].t c.c.c.core2.register.out_ortrees_t[20].tmp[97] c.c.c.core1.slice_pre_dec.in_vt.OR2_tf[0].b c.c1_dec_req_y[128] c.c.c.core2.register.input_valid.OR2_tf[8].b c.c.c.core2.register.registers[38].out_valid.ct.tmp[35] c.c1_reg_data[23].d[4].t c.c1_reg_data[38].d[12].t c.c2_dec_req_y[221] c.c2_dec_req_y[311] c.c.c.core2.register.registers[58].out_valid.ct.in[20] c.c.c.core1.decoder.d_dr_y.atree[242].tmp[11] c.c.c.core2.register.and_reads_f[1150].b c.c.c.core2.register.registers[4].buf._flushBX[0] c.c.c.core1.decoder.d_dr_y.atree[263].tmp[11] c.c2_reg_data[37].d[7].f c.c.c.fifo_dmx2core2.fifo_element[0].t_buf_func[12].y c.c2_syn_mon_y[36] c.c.c.core1.register.registers[59].buf.f_buf_func[8]._y c.c.c.merge_drop8core.in1ack_ctl._y c.c.c.core2.register.registers[15].gandalf_t[21].y c.c2_reg_data[4].d[18].t c.c1_reg_data[12].d[2].f c.c.c.core1.decoder.d_dr_y.atree[1].tmp[11] c.c.c.core2.decoder.dly.dly[6].y c.c.c.core2.register.registers[22].out_valid.ct.tmp[39] c.c.c.core2.register.registers[1].buf._flushBX[0] c.c.c.core1.register.and_reads_t[847]._y c.c1_dec_req_y[26] c.c1_dec_req_y[44] c.c.c.core2.register.registers[59].gandalf_f[9].y c.c.c.core2.register.registers[14].buf.vc.ct.in[19] c.c.c.core1.register.registers[30].gandalf_f[19].y c.c.c.core2.register.out_ortrees_t[4].tmp[117] c.c.c.core2.register.registers[5].gandalf_t[16].y c.c1_reg_data[33].d[9].t c.c1_syn_mon_y[300] c.c1_reg_data[19].d[9].t c.c.c.core2.encoder.Xarb.arbs[12]._y1_arb c.c.c.core2.syn_mon_dec_y.decoder.atree[119].tmp[13] c.c.c.core1.register.and_reads_f[207].b c.c1_dec_req_y[201] c.c2_reg_data[36].d[9].t c.c.c.core2.register.registers[63].buf.en_buf.out[0] c.c.c.core2.register.registers[10].buf.vc.ct.in[20] c.c1_reg_data[34].d[1].t c.c1_reg_data[40].d[19].f c.c.c.core1.register.registers[40].buf.vc.ct.in[12] c.c1_syn_mon_y[15] c.c.c.core1._demux.demux.demux._reset_BXX[0] c.c2_reg_data[12].d[16].t c.in.d[7] c.c.c.core2.register.registers[22].buf.vc.ct.in[9] c.c.c.core1.register.registers[59].buf._flushBX[0] c.c.c.core1.syn_mon_dec_y.decoder.in_tX[3].y c.c2_syn_mon_y[276] c.c1_syn_mon_y[221] c.c.c.core1.register.and_reads_f[335].y c.c.c.core2.register.registers[45].passX.out[0] c.c.c.core1.register.registers[60].gandalf_f[5].y c.c1_syn_mon_y[192] c.c.c.core2.decoder.addr_buf.vc.ct.tmp[20] c.c2_reg_data[4].d[16].t c.c2_dec_req_y[86] c.c.c.core2.register.registers[60].passX.out[0] c.c.c.core2.register.registers[43].gandalf_f[15].y c.c.c.core2.register.registers[35].gandalf_f[19].y c.c1_reg_data[47].d[7].f c.c.c.fifo_fork2drop.fifo_element[2]._reset_BXX[0] c.c.c.core1.decoder.d_dr_y.in_fX[19].y c.c.c.core1.register.registers[8].gandalf_t[17].y c.c.c.core2.register.and_reads_t[370]._y c.c.c.core2.register.registers[58].gandalf_t[17].y c.c1_reg_data[32].d[6].f c.c.c.core1.register.decoder.atree[4].and3s[0]._y c.c.c.core1.register.and_reads_f[273]._y c.c.c.core2.decoder.d_dr_y.in_tX[5].y c.c2_reg_data[60].d[3].t c.c.c.fifo_dmx2core1.fifo_element[2].t_buf_func[22].y c.c.c.core2.register.and_reads_f[1334].b c.c1_dec_req_y[122] c.c2_dec_req_y[186] c.c.c.core2.encoder.buf.t_buf_func[4].y c.c2_reg_data[58].d[9].f c.c.c.core2.syn_mon_dec_y.decoder.atree[253].and2s[1]._y c.c.c.core2.register.registers[52].gandalf_t[2].y c.c1_reg_data[12].d[16].t c.c2_dec_req_y[257] c.c.c.core2.fifo_in.fifo_element[1].en_buf.out[0] c.c.c.core1.register.registers[7Line truncated

test/unit_tests/texel_dualcore_innovus/test.act

@@ -49,7 +49,7 @@ pint NC_NRN_Y = 3;
 
 pint N_SYN_X = 15;
 pint N_SYN_Y = 348;
-pint NC_SYN_X = 6;
+pint NC_SYN_X = 4;
 pint NC_SYN_Y = 9;
 
 pint N_SYN_DLY_CFG = 4;
@@ -63,7 +63,7 @@ pint N_SYN_MON_X = N_SYN_X*4; // [mon, dev_mon, set, reset]*N
 pint N_SYN_MON_Y = N_SYN_Y; //  [mon]*N
 
 pint N_MON_AMZO_PER_SYN = 5;
-pint N_MON_AMZO_PER_NRN = 7;
+pint N_MON_AMZO_PER_NRN = 3;
 
 pint N_FLAGS_PER_SYN = 4; // Syn: Must be at least 3 (since those ones have special safety)
 pint N_FLAGS_PER_NRN = 9; // and leq than the number of bits in a reg, since have presumed only needs one.
@@ -81,9 +81,6 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
 
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-
     bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
     bool? c1_dec_ackB[N_SYN_X];
     a1of1 c1_syn_pu[N_SYN_X];
@@ -97,10 +94,10 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
     bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
-    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
 
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
 
     bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
     bool? c2_dec_ackB[N_SYN_X];
@@ -115,9 +112,13 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
     bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
-    bool? reset_B, reset_reg_B;
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI;
+
     bool vss, vdd
     ){
 
@@ -140,9 +141,9 @@ defproc chip_texel_dualcore_innovus (bd<N_IN> in, out;
     N_LINE_PD_DLY,
     N_BD_DLY_CFG, N_BD_DLY_CFG2,
     REG_NCA, REG_NCW, REG_M> c(.in = in, .out = out,
-        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2,
-        .loopback_en = loopback_en, .supply = supply, .reset_B = reset_B, .reset_reg_B = reset_reg_B);
-
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .c1_reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .c1_reset_syn_hs_BO = c1_reset_syn_hs_BO, .c1_reset_nrn_stge_BO = c1_reset_nrn_stge_BO, .c1_reset_syn_stge_BO = c1_reset_syn_stge_BO, .c2_reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .c2_reset_syn_hs_BO = c2_reset_syn_hs_BO, .c2_reset_nrn_stge_BO = c2_reset_nrn_stge_BO, .c2_reset_syn_stge_BO = c2_reset_syn_stge_BO,
+        .loopback_en = loopback_en, .supply = supply,
+        .reset_B = reset_B, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI);
 }
 
 
@@ -151,9 +152,6 @@ defproc chip_texel_dualcore_innovus_test (bd<N_IN> in, out;
 
     Mx1of2<REG_NCW> c1_reg_data[REG_M];
 
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-
     bool! c1_dec_req_x[N_SYN_X], c1_dec_req_y[N_SYN_Y];
     bool? c1_dec_ackB[N_SYN_X];
     a1of1 c1_syn_pu[N_SYN_X];
@@ -167,10 +165,10 @@ defproc chip_texel_dualcore_innovus_test (bd<N_IN> in, out;
     bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
-    Mx1of2<REG_NCW> c2_reg_data[REG_M];
+    bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
+    c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
 
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
+    Mx1of2<REG_NCW> c2_reg_data[REG_M];
 
     bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
     bool? c2_dec_ackB[N_SYN_X];
@@ -185,9 +183,12 @@ defproc chip_texel_dualcore_innovus_test (bd<N_IN> in, out;
     bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
     bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
 
+    bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
+    c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
+
     bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
     bool? loopback_en;
-    bool? reset_B, reset_reg_B
+    bool? reset_B, reset_reg_B, reset_syn_stge_BI
     ){
     
     power supply;
@@ -195,48 +196,11 @@ defproc chip_texel_dualcore_innovus_test (bd<N_IN> in, out;
     supply.vss = GND;
  
    
-    chip_texel_dualcore_innovus c(.in=in, .out=out,
-
-    .c1_reg_data=c1_reg_data,
-
-    // a1of1 c1_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c1_neurons[N_NRN_X * N_NRN_Y];
-
-    .c1_dec_req_x=c1_dec_req_x, .c1_dec_req_y=c1_dec_req_y,
-    .c1_dec_ackB=c1_dec_ackB,
-    .c1_syn_pu=c1_syn_pu,
-
-    .c1_enc_inx=c1_enc_inx, .c1_enc_iny=c1_enc_iny,
-    .c1_nrn_pd_x=c1_nrn_pd_x, .c1_nrn_pd_y=c1_nrn_pd_y,
-    
-    .c1_nrn_mon_x=c1_nrn_mon_x, .c1_nrn_mon_y=c1_nrn_mon_y,
-    .c1_syn_mon_x=c1_syn_mon_x, .c1_syn_mon_y=c1_syn_mon_y,
-    .c1_syn_mon_AMZI=c1_syn_mon_AMZI, .c1_nrn_mon_AMZI=c1_nrn_mon_AMZI,
-    .c1_syn_mon_AMZO=c1_syn_mon_AMZO, .c1_nrn_mon_AMZO=c1_nrn_mon_AMZO,
-    .c1_syn_flags_EFO=c1_syn_flags_EFO, .c1_nrn_flags_EFO=c1_nrn_flags_EFO,
-
-    .c2_reg_data=c2_reg_data,
-
-    // a1of1 c2_synapses[N_SYN_X * N_SYN_Y];
-    // a1of1 c2_neurons[N_NRN_X * N_NRN_Y];
-
-    .c2_dec_req_x=c2_dec_req_x, .c2_dec_req_y=c2_dec_req_y,
-    .c2_dec_ackB=c2_dec_ackB,
-    .c2_syn_pu=c2_syn_pu,
-
-    .c2_enc_inx=c2_enc_inx, .c2_enc_iny=c2_enc_iny,
-    .c2_nrn_pd_x=c2_nrn_pd_x, .c2_nrn_pd_y=c2_nrn_pd_y,
-    
-    .c2_nrn_mon_x=c2_nrn_mon_x, .c2_nrn_mon_y=c2_nrn_mon_y,
-    .c2_syn_mon_x=c2_syn_mon_x, .c2_syn_mon_y=c2_syn_mon_y,
-    .c2_syn_mon_AMZI=c2_syn_mon_AMZI, .c2_nrn_mon_AMZI=c2_nrn_mon_AMZI,
-    .c2_syn_mon_AMZO=c2_syn_mon_AMZO, .c2_nrn_mon_AMZO=c2_nrn_mon_AMZO,
-    .c2_syn_flags_EFO=c2_syn_flags_EFO, .c2_nrn_flags_EFO=c2_nrn_flags_EFO,
-
-    .bd_dly_cfg=bd_dly_cfg, .bd_dly_cfg2=bd_dly_cfg2,
-    .loopback_en=loopback_en,
-    .reset_B=reset_B, .reset_reg_B=reset_reg_B,
-    .vss=supply.vss, .vdd=supply.vdd
+    chip_texel_dualcore_innovus c(.in = in, .out = out,
+        .c1_reg_data = c1_reg_data, .c1_dec_req_x = c1_dec_req_x, .c1_dec_req_y = c1_dec_req_y, .c1_dec_ackB = c1_dec_ackB, .c1_syn_pu = c1_syn_pu, .c1_enc_inx = c1_enc_inx, .c1_enc_iny = c1_enc_iny, .c1_nrn_pd_x = c1_nrn_pd_x, .c1_nrn_pd_y = c1_nrn_pd_y, .c1_nrn_mon_x = c1_nrn_mon_x, .c1_nrn_mon_y = c1_nrn_mon_y, .c1_syn_mon_x = c1_syn_mon_x, .c1_syn_mon_y = c1_syn_mon_y, .c1_syn_mon_AMZI = c1_syn_mon_AMZI, .c1_nrn_mon_AMZI = c1_nrn_mon_AMZI, .c1_syn_mon_AMZO = c1_syn_mon_AMZO, .c1_nrn_mon_AMZO = c1_nrn_mon_AMZO, .c1_syn_flags_EFO = c1_syn_flags_EFO, .c1_nrn_flags_EFO = c1_nrn_flags_EFO, .c2_reg_data = c2_reg_data, .c2_dec_req_x = c2_dec_req_x, .c2_dec_req_y = c2_dec_req_y, .c2_dec_ackB = c2_dec_ackB, .c2_syn_pu = c2_syn_pu, .c2_enc_inx = c2_enc_inx, .c2_enc_iny = c2_enc_iny, .c2_nrn_pd_x = c2_nrn_pd_x, .c2_nrn_pd_y = c2_nrn_pd_y, .c2_nrn_mon_x = c2_nrn_mon_x, .c2_nrn_mon_y = c2_nrn_mon_y, .c2_syn_mon_x = c2_syn_mon_x, .c2_syn_mon_y = c2_syn_mon_y, .c2_syn_mon_AMZI = c2_syn_mon_AMZI, .c2_nrn_mon_AMZI = c2_nrn_mon_AMZI, .c2_syn_mon_AMZO = c2_syn_mon_AMZO, .c2_nrn_mon_AMZO = c2_nrn_mon_AMZO, .c2_syn_flags_EFO = c2_syn_flags_EFO, .c2_nrn_flags_EFO = c2_nrn_flags_EFO, .bd_dly_cfg = bd_dly_cfg, .bd_dly_cfg2 = bd_dly_cfg2, .c1_reset_nrn_hs_BO = c1_reset_nrn_hs_BO, .c1_reset_syn_hs_BO = c1_reset_syn_hs_BO, .c1_reset_nrn_stge_BO = c1_reset_nrn_stge_BO, .c1_reset_syn_stge_BO = c1_reset_syn_stge_BO, .c2_reset_nrn_hs_BO = c2_reset_nrn_hs_BO, .c2_reset_syn_hs_BO = c2_reset_syn_hs_BO, .c2_reset_nrn_stge_BO = c2_reset_nrn_stge_BO, .c2_reset_syn_stge_BO = c2_reset_syn_stge_BO,
+        .loopback_en = loopback_en,
+        .reset_B = reset_B, .reset_reg_B = reset_reg_B, .reset_syn_stge_BI = reset_syn_stge_BI,
+        .vss=supply.vss, .vdd=supply.vdd
     );
     }