bics/actlib_dataflow_neuro
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regenned texel dualcore innovus fairly finaly??

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This commit is contained in:
alexmadison
2022-05-02 19:45:34 +02:00
parent d3a1a27bb0
commit 10f4821eaa
4 changed files with 1294592 additions and 1263439 deletions
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18
dataflow_neuro/chips.act
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@ -271,7 +271,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
sb_nrn_EFO.in[i] = register.data[5].d[i].t;
)
// Create buffered signals from register to synapses.
// Create buffered signals from register to synapses.
// Includes safety on the first 3 flags with dev mon.
sigbuf_boolarray<N_FLAGS_PER_SYN, 31> sb_syn_EFO(.out = syn_flags_EFO, .supply = supply);
(i:3..N_FLAGS_PER_SYN-1:
@ -281,7 +281,7 @@ defproc texel_core (avMx1of2<N_IN> in, out;
(i:0..2:
syn_flags_dev_safety[i].a = register.data[4].d[i].t; // syn flag bit
syn_flags_dev_safety[i].b = register.data[0].d[5].f; // no device is being monitored.
sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y
sb_syn_EFO.in[i] = syn_flags_dev_safety[i].y;
syn_flags_dev_safety[i].vdd = supply.vdd;
syn_flags_dev_safety[i].vss = supply.vss;
@ -412,6 +412,9 @@ defproc texel_dualcore (bd<N_IN> in, out;
bool! c1_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c1_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c1_syn_flags_EFO[N_FLAGS_PER_SYN], c1_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
Mx1of2<REG_NCW> c2_reg_data[REG_M];
bool! c2_dec_req_x[N_SYN_X], c2_dec_req_y[N_SYN_Y];
@ -427,16 +430,13 @@ defproc texel_dualcore (bd<N_IN> in, out;
bool! c2_syn_mon_AMZO[N_MON_AMZO_PER_SYN], c2_nrn_mon_AMZO[N_MON_AMZO_PER_NRN];
bool! c2_syn_flags_EFO[N_FLAGS_PER_SYN], c2_nrn_flags_EFO[N_FLAGS_PER_NRN];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X];
bool? bd_dly_cfg[N_BD_DLY_CFG], bd_dly_cfg2[N_BD_DLY_CFG2];
bool? loopback_en;
power supply;
bool? reset_B, reset_reg_B, reset_syn_stge_BI;
bool! c1_reset_nrn_hs_BO[N_NRN_X], c1_reset_syn_hs_BO[N_SYN_X],
c1_reset_nrn_stge_BO[N_NRN_X], c1_reset_syn_stge_BO[N_SYN_X];
bool! c2_reset_nrn_hs_BO[N_NRN_X], c2_reset_syn_hs_BO[N_SYN_X],
c2_reset_nrn_stge_BO[N_NRN_X], c2_reset_syn_stge_BO[N_SYN_X]
bool? reset_B, reset_reg_B, reset_syn_stge_BI
){
// Reset buffers