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Added stuff for line end pull U/D

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Greatorex 2022-03-04 12:33:49 +01:00
parent 0e9f2ae506
commit 1abcc9dc55
7 changed files with 843 additions and 0 deletions
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13
dataflow_neuro/cell_lib_async.act
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@ -524,6 +524,19 @@ namespace tmpl {
mk_excllo(_y1, _y2)
}
}
defproc PULLDOWN_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] a -> y-
}
}
defproc PULLUP_X4(bool? a; bool! y; bool? vdd, vss)
{
prs{
[keeper=0] ~a -> y+
}
}
}}

23
dataflow_neuro/primitives.act
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@ -673,4 +673,27 @@ namespace tmpl {
(i:N:mu2[i].vss = supply.vss;)
(i:((1<<N)-1):dly[i].vss = supply.vss;)
}
export
defproc line_end_pull_up (a1of1 in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nor_out;
BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
PULLUP_X4 pull_up(.a=nor_out, .y=out);
}
defproc line_end_pull_down (a1of1 in; bool? reset_B; power supply; bool! out)
{
bool _out, __out, nor_out;
BUF_X4 buf1(.a=in.a, .y=_out, .vdd=supply.vdd,.vss=supply.vss);
BUF_X4 buf2(.a=_out, .y=__out, .vdd=supply.vdd,.vss=supply.vss);
NOR2_X1 aenor(.a=_out, .b=reset_B, .y = nor_out, .vdd=supply.vdd,.vss=supply.vss);
PULLUP_X4 pull_down(.a=nor_out, .y=out);
}
}}

685
test/unit_tests/buf_15.v Normal file
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@ -0,0 +1,685 @@
//
// Verilog module for: BUF_X6<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X6(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: sigbuf<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4(in, \out[0] );
input in;
output \out[0] ;
// -- signals ---
wire in;
reg \out[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X6 \buf6 (.y(\out[0] ), .a(in));
endmodule
//
// Verilog module for: A_3C_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4(y, c1, c2, c3, pr_B, sr_B);
output y;
input c1;
input c2;
input c3;
input pr_B;
input sr_B;
// -- signals ---
wire sr_B;
wire pr_B;
wire c3;
wire c1;
reg _y;
reg y;
wire c2;
// --- instances
endmodule
//
// Verilog module for: BUF_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X4(y, a);
output y;
input a;
// -- signals ---
reg _y;
wire a;
reg y;
// --- instances
endmodule
//
// Verilog module for: INV_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0INV__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
// --- instances
endmodule
//
// Verilog module for: A_2C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1(y, c1, c2);
output y;
input c1;
input c2;
// -- signals ---
reg y;
reg _y;
wire c2;
wire c1;
// --- instances
endmodule
//
// Verilog module for: A_3C_B_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1(y, c1, c2, c3);
output y;
input c1;
input c2;
input c3;
// -- signals ---
reg _y;
reg y;
wire c3;
wire c1;
wire c2;
// --- instances
endmodule
//
// Verilog module for: ctree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4(\in[0] , \in[1] , \in[2] , \in[3] , \in[4] , \in[5] , \in[6] , \in[7] , \in[8] , \in[9] , \in[10] , \in[11] , \in[12] , \in[13] , \in[14] , out);
input \in[0] ;
input \in[1] ;
input \in[2] ;
input \in[3] ;
input \in[4] ;
input \in[5] ;
input \in[6] ;
input \in[7] ;
input \in[8] ;
input \in[9] ;
input \in[10] ;
input \in[11] ;
input \in[12] ;
input \in[13] ;
input \in[14] ;
output out;
// -- signals ---
wire \in[4] ;
wire \in[11] ;
wire \in[12] ;
reg \tmp[21] ;
wire \in[3] ;
reg out;
reg \tmp[23] ;
wire \in[6] ;
wire \in[0] ;
reg \tmp[18] ;
wire \in[10] ;
reg \tmp[15] ;
reg \tmp[16] ;
wire \in[13] ;
wire \in[1] ;
wire \in[9] ;
wire \in[2] ;
wire \in[5] ;
reg \tmp[24] ;
wire \in[14] ;
reg \tmp[19] ;
wire \in[7] ;
reg \tmp[22] ;
reg \tmp[20] ;
wire \in[8] ;
reg \tmp[17] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[0] (.y(\tmp[15] ), .c1(\in[0] ), .c2(\in[1] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[1] (.y(\tmp[16] ), .c1(\in[2] ), .c2(\in[3] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[2] (.y(\tmp[17] ), .c1(\in[4] ), .c2(\in[5] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[3] (.y(\tmp[18] ), .c1(\in[6] ), .c2(\in[7] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[4] (.y(\tmp[19] ), .c1(\in[8] ), .c2(\in[9] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[5] (.y(\tmp[20] ), .c1(\in[10] ), .c2(\in[11] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[6] (.y(\tmp[22] ), .c1(\tmp[15] ), .c2(\tmp[16] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C__B__X1 \C2Els[7] (.y(\tmp[23] ), .c1(\tmp[17] ), .c2(\tmp[18] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[0] (.y(\tmp[21] ), .c1(\in[12] ), .c2(\in[13] ), .c3(\in[14] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[1] (.y(\tmp[24] ), .c1(\tmp[19] ), .c2(\tmp[20] ), .c3(\tmp[21] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__B__X1 \C3Els[2] (.y(out), .c1(\tmp[22] ), .c2(\tmp[23] ), .c3(\tmp[24] ));
endmodule
//
// Verilog module for: OR2_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0OR2__X1(y, a, b);
output y;
input a;
input b;
// -- signals ---
reg y;
wire a;
reg _y;
wire b;
// --- instances
endmodule
//
// Verilog module for: vtree<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4(\in.d[0].d[0] , \in.d[0].d[1] , \in.d[1].d[0] , \in.d[1].d[1] , \in.d[2].d[0] , \in.d[2].d[1] , \in.d[3].d[0] , \in.d[3].d[1] , \in.d[4].d[0] , \in.d[4].d[1] , \in.d[5].d[0] , \in.d[5].d[1] , \in.d[6].d[0] , \in.d[6].d[1] , \in.d[7].d[0] , \in.d[7].d[1] , \in.d[8].d[0] , \in.d[8].d[1] , \in.d[9].d[0] , \in.d[9].d[1] , \in.d[10].d[0] , \in.d[10].d[1] , \in.d[11].d[0] , \in.d[11].d[1] , \in.d[12].d[0] , \in.d[12].d[1] , \in.d[13].d[0] , \in.d[13].d[1] , \in.d[14].d[0] , \in.d[14].d[1] , out);
input \in.d[0].d[0] ;
input \in.d[0].d[1] ;
input \in.d[1].d[0] ;
input \in.d[1].d[1] ;
input \in.d[2].d[0] ;
input \in.d[2].d[1] ;
input \in.d[3].d[0] ;
input \in.d[3].d[1] ;
input \in.d[4].d[0] ;
input \in.d[4].d[1] ;
input \in.d[5].d[0] ;
input \in.d[5].d[1] ;
input \in.d[6].d[0] ;
input \in.d[6].d[1] ;
input \in.d[7].d[0] ;
input \in.d[7].d[1] ;
input \in.d[8].d[0] ;
input \in.d[8].d[1] ;
input \in.d[9].d[0] ;
input \in.d[9].d[1] ;
input \in.d[10].d[0] ;
input \in.d[10].d[1] ;
input \in.d[11].d[0] ;
input \in.d[11].d[1] ;
input \in.d[12].d[0] ;
input \in.d[12].d[1] ;
input \in.d[13].d[0] ;
input \in.d[13].d[1] ;
input \in.d[14].d[0] ;
input \in.d[14].d[1] ;
output out;
// -- signals ---
reg \ct.in[14] ;
reg \ct.in[13] ;
wire \in.d[7].d[0] ;
wire \in.d[1].d[0] ;
wire \in.d[0].d[0] ;
reg \ct.in[4] ;
reg out;
wire \in.d[10].d[0] ;
wire \in.d[4].d[1] ;
reg \ct.in[3] ;
wire \in.d[9].d[1] ;
wire \in.d[1].d[1] ;
wire \in.d[2].d[0] ;
wire \in.d[10].d[1] ;
reg \ct.in[8] ;
wire \in.d[12].d[0] ;
wire \in.d[5].d[0] ;
wire \in.d[4].d[0] ;
reg \ct.in[10] ;
reg \ct.in[0] ;
wire \in.d[11].d[0] ;
wire \in.d[7].d[1] ;
wire \in.d[3].d[1] ;
reg \ct.in[11] ;
reg \ct.in[2] ;
reg \ct.in[9] ;
wire \in.d[13].d[0] ;
wire \in.d[14].d[1] ;
wire \in.d[11].d[1] ;
wire \in.d[13].d[1] ;
wire \in.d[0].d[1] ;
reg \ct.in[1] ;
wire \in.d[14].d[0] ;
wire \in.d[12].d[1] ;
wire \in.d[9].d[0] ;
wire \in.d[2].d[1] ;
reg \ct.in[5] ;
wire \in.d[5].d[1] ;
reg \ct.in[12] ;
reg \ct.in[6] ;
wire \in.d[3].d[0] ;
wire \in.d[8].d[0] ;
wire \in.d[8].d[1] ;
reg \ct.in[7] ;
wire \in.d[6].d[0] ;
wire \in.d[6].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0ctree_315_4 \ct (.\in[0] (\ct.in[0] ), .\in[1] (\ct.in[1] ), .\in[2] (\ct.in[2] ), .\in[3] (\ct.in[3] ), .\in[4] (\ct.in[4] ), .\in[5] (\ct.in[5] ), .\in[6] (\ct.in[6] ), .\in[7] (\ct.in[7] ), .\in[8] (\ct.in[8] ), .\in[9] (\ct.in[9] ), .\in[10] (\ct.in[10] ), .\in[11] (\ct.in[11] ), .\in[12] (\ct.in[12] ), .\in[13] (\ct.in[13] ), .\in[14] (\ct.in[14] ), .out(out));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[0] (.y(\ct.in[0] ), .a(\in.d[0].d[1] ), .b(\in.d[0].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[1] (.y(\ct.in[1] ), .a(\in.d[1].d[1] ), .b(\in.d[1].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[2] (.y(\ct.in[2] ), .a(\in.d[2].d[1] ), .b(\in.d[2].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[3] (.y(\ct.in[3] ), .a(\in.d[3].d[1] ), .b(\in.d[3].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[4] (.y(\ct.in[4] ), .a(\in.d[4].d[1] ), .b(\in.d[4].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[5] (.y(\ct.in[5] ), .a(\in.d[5].d[1] ), .b(\in.d[5].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[6] (.y(\ct.in[6] ), .a(\in.d[6].d[1] ), .b(\in.d[6].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[7] (.y(\ct.in[7] ), .a(\in.d[7].d[1] ), .b(\in.d[7].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[8] (.y(\ct.in[8] ), .a(\in.d[8].d[1] ), .b(\in.d[8].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[9] (.y(\ct.in[9] ), .a(\in.d[9].d[1] ), .b(\in.d[9].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[10] (.y(\ct.in[10] ), .a(\in.d[10].d[1] ), .b(\in.d[10].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[11] (.y(\ct.in[11] ), .a(\in.d[11].d[1] ), .b(\in.d[11].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[12] (.y(\ct.in[12] ), .a(\in.d[12].d[1] ), .b(\in.d[12].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[13] (.y(\ct.in[13] ), .a(\in.d[13].d[1] ), .b(\in.d[13].d[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0OR2__X1 \OR2_tf[14] (.y(\ct.in[14] ), .a(\in.d[14].d[1] ), .b(\in.d[14].d[0] ));
endmodule
//
// Verilog module for: A_1C1P_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1(y, c1, p1);
output y;
input c1;
input p1;
// -- signals ---
reg y;
wire c1;
wire p1;
// --- instances
endmodule
//
// Verilog module for: BUF_X1<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0BUF__X1(y, a);
output y;
input a;
// -- signals ---
reg y;
wire a;
reg _y;
// --- instances
endmodule
//
// Verilog module for: A_2C1N_RB_X4<>
//
module _0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4(y, c1, c2, n1, pr_B, sr_B);
output y;
input c1;
input c2;
input n1;
input pr_B;
input sr_B;
// -- signals ---
reg y;
wire pr_B;
wire c2;
wire n1;
wire c1;
reg _y;
wire sr_B;
// --- instances
endmodule
//
// Verilog module for: buffer<15>
//
module _0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v , reset_B);
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
input reset_B;
// -- signals ---
reg \out.d.d[8].d[0] ;
reg \out.d.d[6].d[1] ;
reg \out.d.d[5].d[1] ;
reg \_en_X_f[0] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[12].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[7].d[0] ;
reg _reset_BX;
reg \_reset_BXX[0] ;
wire \in.d.d[14].d[1] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[2].d[0] ;
wire \out.a ;
reg \out.d.d[0].d[0] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[7].d[1] ;
wire \in.d.d[3].d[1] ;
reg _in_v;
reg \in.v ;
reg _out_a_B;
wire \in.d.d[9].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[10].d[0] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[1].d[0] ;
reg \_out_a_BX_f[0] ;
reg \out.d.d[3].d[1] ;
reg \out.d.d[0].d[1] ;
reg \out.d.d[2].d[1] ;
reg \out.d.d[4].d[1] ;
wire reset_B;
wire \in.d.d[8].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[5].d[1] ;
reg \out.d.d[9].d[0] ;
reg \out.d.d[7].d[1] ;
reg \_out_a_BX_t[0] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[6].d[0] ;
wire \in.d.d[7].d[0] ;
wire \in.d.d[13].d[1] ;
wire \out.v ;
reg \out.d.d[2].d[0] ;
wire \in.d.d[13].d[0] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[3].d[0] ;
reg \out.d.d[11].d[1] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
reg _en;
reg \out.d.d[13].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[14].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[6].d[0] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[1].d[1] ;
reg \_en_X_t[0] ;
wire \in.d.d[0].d[1] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_t (.in(_out_a_B), .\out[0] (\_out_a_BX_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__3C__RB__X4 \inack_ctl (.y(\in.a ), .c1(_en), .c2(\in.v ), .c3(\out.v ), .pr_B(_reset_BX), .sr_B(_reset_BX));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \reset_bufarray (.in(_reset_BX), .\out[0] (\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X4 \in_v_buf (.y(\in.v ), .a(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0INV__X1 \out_a_inv (.y(_out_a_B), .a(\out.a ));
_0_0tmpl_0_0dataflow__neuro_0_0vtree_315_4 \vc (.\in.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d[14].d[1] (\in.d.d[14].d[1] ), .out(_in_v));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \out_a_B_buf_f (.in(_out_a_B), .\out[0] (\_out_a_BX_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__1C1P__X1 \en_ctl (.y(_en), .c1(\in.a ), .p1(\out.v ));
_0_0tmpl_0_0dataflow__neuro_0_0BUF__X1 \reset_buf (.y(_reset_BX), .a(reset_B));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_f (.in(_en), .\out[0] (\_en_X_f[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0sigbuf_315_4 \en_buf_t (.in(_en), .\out[0] (\_en_X_t[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[0] (.y(\out.d.d[0].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[0].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[1] (.y(\out.d.d[1].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[1].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[2] (.y(\out.d.d[2].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[2].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[3] (.y(\out.d.d[3].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[3].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[4] (.y(\out.d.d[4].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[4].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[5] (.y(\out.d.d[5].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[5].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[6] (.y(\out.d.d[6].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[6].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[7] (.y(\out.d.d[7].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[7].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[8] (.y(\out.d.d[8].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[8].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[9] (.y(\out.d.d[9].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[9].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[10] (.y(\out.d.d[10].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[10].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[11] (.y(\out.d.d[11].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[11].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[12] (.y(\out.d.d[12].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[12].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[13] (.y(\out.d.d[13].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[13].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \t_buf_func[14] (.y(\out.d.d[14].d[1] ), .c1(\_en_X_t[0] ), .c2(\_out_a_BX_t[0] ), .n1(\in.d.d[14].d[1] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[0] (.y(\out.d.d[0].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[0].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[1] (.y(\out.d.d[1].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[1].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[2] (.y(\out.d.d[2].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[2].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[3] (.y(\out.d.d[3].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[3].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[4] (.y(\out.d.d[4].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[4].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[5] (.y(\out.d.d[5].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[5].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[6] (.y(\out.d.d[6].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[6].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[7] (.y(\out.d.d[7].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[7].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[8] (.y(\out.d.d[8].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[8].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[9] (.y(\out.d.d[9].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[9].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[10] (.y(\out.d.d[10].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[10].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[11] (.y(\out.d.d[11].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[11].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[12] (.y(\out.d.d[12].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[12].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[13] (.y(\out.d.d[13].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[13].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
_0_0tmpl_0_0dataflow__neuro_0_0A__2C1N__RB__X4 \f_buf_func[14] (.y(\out.d.d[14].d[0] ), .c1(\_en_X_f[0] ), .c2(\_out_a_BX_f[0] ), .n1(\in.d.d[14].d[0] ), .pr_B(\_reset_BXX[0] ), .sr_B(\_reset_BXX[0] ));
endmodule
//
// Verilog module for: buffer_15<>
//
module buffer__15(\in.d.d[0].d[0] , \in.d.d[0].d[1] , \in.d.d[1].d[0] , \in.d.d[1].d[1] , \in.d.d[2].d[0] , \in.d.d[2].d[1] , \in.d.d[3].d[0] , \in.d.d[3].d[1] , \in.d.d[4].d[0] , \in.d.d[4].d[1] , \in.d.d[5].d[0] , \in.d.d[5].d[1] , \in.d.d[6].d[0] , \in.d.d[6].d[1] , \in.d.d[7].d[0] , \in.d.d[7].d[1] , \in.d.d[8].d[0] , \in.d.d[8].d[1] , \in.d.d[9].d[0] , \in.d.d[9].d[1] , \in.d.d[10].d[0] , \in.d.d[10].d[1] , \in.d.d[11].d[0] , \in.d.d[11].d[1] , \in.d.d[12].d[0] , \in.d.d[12].d[1] , \in.d.d[13].d[0] , \in.d.d[13].d[1] , \in.d.d[14].d[0] , \in.d.d[14].d[1] , \in.a , \in.v , \out.d.d[0].d[0] , \out.d.d[0].d[1] , \out.d.d[1].d[0] , \out.d.d[1].d[1] , \out.d.d[2].d[0] , \out.d.d[2].d[1] , \out.d.d[3].d[0] , \out.d.d[3].d[1] , \out.d.d[4].d[0] , \out.d.d[4].d[1] , \out.d.d[5].d[0] , \out.d.d[5].d[1] , \out.d.d[6].d[0] , \out.d.d[6].d[1] , \out.d.d[7].d[0] , \out.d.d[7].d[1] , \out.d.d[8].d[0] , \out.d.d[8].d[1] , \out.d.d[9].d[0] , \out.d.d[9].d[1] , \out.d.d[10].d[0] , \out.d.d[10].d[1] , \out.d.d[11].d[0] , \out.d.d[11].d[1] , \out.d.d[12].d[0] , \out.d.d[12].d[1] , \out.d.d[13].d[0] , \out.d.d[13].d[1] , \out.d.d[14].d[0] , \out.d.d[14].d[1] , \out.a , \out.v );
input \in.d.d[0].d[0] ;
input \in.d.d[0].d[1] ;
input \in.d.d[1].d[0] ;
input \in.d.d[1].d[1] ;
input \in.d.d[2].d[0] ;
input \in.d.d[2].d[1] ;
input \in.d.d[3].d[0] ;
input \in.d.d[3].d[1] ;
input \in.d.d[4].d[0] ;
input \in.d.d[4].d[1] ;
input \in.d.d[5].d[0] ;
input \in.d.d[5].d[1] ;
input \in.d.d[6].d[0] ;
input \in.d.d[6].d[1] ;
input \in.d.d[7].d[0] ;
input \in.d.d[7].d[1] ;
input \in.d.d[8].d[0] ;
input \in.d.d[8].d[1] ;
input \in.d.d[9].d[0] ;
input \in.d.d[9].d[1] ;
input \in.d.d[10].d[0] ;
input \in.d.d[10].d[1] ;
input \in.d.d[11].d[0] ;
input \in.d.d[11].d[1] ;
input \in.d.d[12].d[0] ;
input \in.d.d[12].d[1] ;
input \in.d.d[13].d[0] ;
input \in.d.d[13].d[1] ;
input \in.d.d[14].d[0] ;
input \in.d.d[14].d[1] ;
output \in.a ;
output \in.v ;
output \out.d.d[0].d[0] ;
output \out.d.d[0].d[1] ;
output \out.d.d[1].d[0] ;
output \out.d.d[1].d[1] ;
output \out.d.d[2].d[0] ;
output \out.d.d[2].d[1] ;
output \out.d.d[3].d[0] ;
output \out.d.d[3].d[1] ;
output \out.d.d[4].d[0] ;
output \out.d.d[4].d[1] ;
output \out.d.d[5].d[0] ;
output \out.d.d[5].d[1] ;
output \out.d.d[6].d[0] ;
output \out.d.d[6].d[1] ;
output \out.d.d[7].d[0] ;
output \out.d.d[7].d[1] ;
output \out.d.d[8].d[0] ;
output \out.d.d[8].d[1] ;
output \out.d.d[9].d[0] ;
output \out.d.d[9].d[1] ;
output \out.d.d[10].d[0] ;
output \out.d.d[10].d[1] ;
output \out.d.d[11].d[0] ;
output \out.d.d[11].d[1] ;
output \out.d.d[12].d[0] ;
output \out.d.d[12].d[1] ;
output \out.d.d[13].d[0] ;
output \out.d.d[13].d[1] ;
output \out.d.d[14].d[0] ;
output \out.d.d[14].d[1] ;
input \out.a ;
input \out.v ;
// -- signals ---
reg \out.d.d[2].d[1] ;
wire \in.d.d[10].d[0] ;
reg \out.d.d[1].d[0] ;
wire \in.d.d[10].d[1] ;
wire \in.d.d[4].d[0] ;
reg \out.d.d[10].d[1] ;
wire \in.d.d[13].d[0] ;
reg \out.d.d[13].d[0] ;
reg \out.d.d[9].d[1] ;
wire \in.d.d[2].d[1] ;
reg \out.d.d[2].d[0] ;
reg \out.d.d[0].d[0] ;
reg \out.d.d[14].d[0] ;
reg \out.d.d[5].d[0] ;
reg \in.a ;
reg _reset_B;
wire \out.v ;
wire \out.a ;
reg \out.d.d[4].d[0] ;
wire \in.d.d[9].d[1] ;
wire \in.d.d[3].d[0] ;
wire \in.d.d[11].d[0] ;
wire \in.d.d[2].d[0] ;
reg \out.d.d[6].d[0] ;
reg \out.d.d[13].d[1] ;
reg \out.d.d[10].d[0] ;
reg \out.d.d[7].d[1] ;
wire \in.d.d[12].d[1] ;
wire \in.d.d[6].d[1] ;
reg \out.d.d[7].d[0] ;
reg \out.d.d[3].d[0] ;
wire \in.d.d[1].d[0] ;
reg \out.d.d[14].d[1] ;
reg \out.d.d[8].d[0] ;
wire \in.d.d[13].d[1] ;
wire \in.d.d[7].d[0] ;
reg \out.d.d[12].d[0] ;
wire \in.d.d[8].d[1] ;
reg \out.d.d[4].d[1] ;
wire \in.d.d[14].d[0] ;
wire \in.d.d[5].d[1] ;
wire \in.d.d[1].d[1] ;
wire \in.d.d[9].d[0] ;
wire \in.d.d[14].d[1] ;
reg \out.d.d[11].d[0] ;
reg \out.d.d[6].d[1] ;
wire \in.d.d[12].d[0] ;
wire \in.d.d[7].d[1] ;
reg \out.d.d[0].d[1] ;
wire \in.d.d[11].d[1] ;
wire \in.d.d[8].d[0] ;
wire \in.d.d[5].d[0] ;
reg \out.d.d[1].d[1] ;
reg \in.v ;
wire \in.d.d[0].d[1] ;
wire \in.d.d[0].d[0] ;
reg \out.d.d[5].d[1] ;
reg \out.d.d[8].d[1] ;
reg \out.d.d[3].d[1] ;
wire \in.d.d[6].d[0] ;
reg \out.d.d[11].d[1] ;
wire \in.d.d[3].d[1] ;
reg \out.d.d[12].d[1] ;
wire \in.d.d[4].d[1] ;
reg \out.d.d[9].d[0] ;
// --- instances
_0_0tmpl_0_0dataflow__neuro_0_0buffer_315_4 \buffer_test (.\in.d.d[0].d[0] (\in.d.d[0].d[0] ), .\in.d.d[0].d[1] (\in.d.d[0].d[1] ), .\in.d.d[1].d[0] (\in.d.d[1].d[0] ), .\in.d.d[1].d[1] (\in.d.d[1].d[1] ), .\in.d.d[2].d[0] (\in.d.d[2].d[0] ), .\in.d.d[2].d[1] (\in.d.d[2].d[1] ), .\in.d.d[3].d[0] (\in.d.d[3].d[0] ), .\in.d.d[3].d[1] (\in.d.d[3].d[1] ), .\in.d.d[4].d[0] (\in.d.d[4].d[0] ), .\in.d.d[4].d[1] (\in.d.d[4].d[1] ), .\in.d.d[5].d[0] (\in.d.d[5].d[0] ), .\in.d.d[5].d[1] (\in.d.d[5].d[1] ), .\in.d.d[6].d[0] (\in.d.d[6].d[0] ), .\in.d.d[6].d[1] (\in.d.d[6].d[1] ), .\in.d.d[7].d[0] (\in.d.d[7].d[0] ), .\in.d.d[7].d[1] (\in.d.d[7].d[1] ), .\in.d.d[8].d[0] (\in.d.d[8].d[0] ), .\in.d.d[8].d[1] (\in.d.d[8].d[1] ), .\in.d.d[9].d[0] (\in.d.d[9].d[0] ), .\in.d.d[9].d[1] (\in.d.d[9].d[1] ), .\in.d.d[10].d[0] (\in.d.d[10].d[0] ), .\in.d.d[10].d[1] (\in.d.d[10].d[1] ), .\in.d.d[11].d[0] (\in.d.d[11].d[0] ), .\in.d.d[11].d[1] (\in.d.d[11].d[1] ), .\in.d.d[12].d[0] (\in.d.d[12].d[0] ), .\in.d.d[12].d[1] (\in.d.d[12].d[1] ), .\in.d.d[13].d[0] (\in.d.d[13].d[0] ), .\in.d.d[13].d[1] (\in.d.d[13].d[1] ), .\in.d.d[14].d[0] (\in.d.d[14].d[0] ), .\in.d.d[14].d[1] (\in.d.d[14].d[1] ), .\in.a (\in.a ), .\in.v (\in.v ), .\out.d.d[0].d[0] (\out.d.d[0].d[0] ), .\out.d.d[0].d[1] (\out.d.d[0].d[1] ), .\out.d.d[1].d[0] (\out.d.d[1].d[0] ), .\out.d.d[1].d[1] (\out.d.d[1].d[1] ), .\out.d.d[2].d[0] (\out.d.d[2].d[0] ), .\out.d.d[2].d[1] (\out.d.d[2].d[1] ), .\out.d.d[3].d[0] (\out.d.d[3].d[0] ), .\out.d.d[3].d[1] (\out.d.d[3].d[1] ), .\out.d.d[4].d[0] (\out.d.d[4].d[0] ), .\out.d.d[4].d[1] (\out.d.d[4].d[1] ), .\out.d.d[5].d[0] (\out.d.d[5].d[0] ), .\out.d.d[5].d[1] (\out.d.d[5].d[1] ), .\out.d.d[6].d[0] (\out.d.d[6].d[0] ), .\out.d.d[6].d[1] (\out.d.d[6].d[1] ), .\out.d.d[7].d[0] (\out.d.d[7].d[0] ), .\out.d.d[7].d[1] (\out.d.d[7].d[1] ), .\out.d.d[8].d[0] (\out.d.d[8].d[0] ), .\out.d.d[8].d[1] (\out.d.d[8].d[1] ), .\out.d.d[9].d[0] (\out.d.d[9].d[0] ), .\out.d.d[9].d[1] (\out.d.d[9].d[1] ), .\out.d.d[10].d[0] (\out.d.d[10].d[0] ), .\out.d.d[10].d[1] (\out.d.d[10].d[1] ), .\out.d.d[11].d[0] (\out.d.d[11].d[0] ), .\out.d.d[11].d[1] (\out.d.d[11].d[1] ), .\out.d.d[12].d[0] (\out.d.d[12].d[0] ), .\out.d.d[12].d[1] (\out.d.d[12].d[1] ), .\out.d.d[13].d[0] (\out.d.d[13].d[0] ), .\out.d.d[13].d[1] (\out.d.d[13].d[1] ), .\out.d.d[14].d[0] (\out.d.d[14].d[0] ), .\out.d.d[14].d[1] (\out.d.d[14].d[1] ), .\out.a (\out.a ), .\out.v (\out.v ), .reset_B(_reset_B));
endmodule

17
test/unit_tests/line_end_pull_up/run/prsim.out Normal file
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@ -0,0 +1,17 @@
t.in.a t.lepu.nor_out t.lepu.__out t.lepu.buf1._y t.lepu._out t.out t.lepu.buf2._y
1 t.in.a : 0
7093 t.lepu.buf1._y : 1 [by t.in.a:=0]
17560 t.lepu._out : 0 [by t.lepu.buf1._y:=1]
17562 t.lepu.nor_out : 1 [by t.lepu._out:=0]
22313 t.lepu.buf2._y : 1 [by t.lepu._out:=0]
23450 t.lepu.__out : 0 [by t.lepu.buf2._y:=1]
yo man
23450 Reset : 0
23564 t._reset_B : 1 [by Reset:=0]
88930 t.lepu.nor_out : 0 [by t._reset_B:=1]
90656 t.out : 1 [by t.lepu.nor_out:=0]
90656 t.in.a : 1
90695 t.lepu.buf1._y : 0 [by t.in.a:=1]
90710 t.lepu._out : 1 [by t.lepu.buf1._y:=0]
91201 t.lepu.buf2._y : 0 [by t.lepu._out:=1]
91214 t.lepu.__out : 1 [by t.lepu.buf2._y:=0]

42
test/unit_tests/line_end_pull_up/run/test.prs Normal file
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@ -0,0 +1,42 @@
= "GND" "GND"
= "Vdd" "Vdd"
= "Reset" "Reset"
"Reset"->"t._reset_B"-
~("Reset")->"t._reset_B"+
= "t._reset_B" "t.lepu.reset_B"
~"t.lepu.pull_up.a"->"t.lepu.pull_up.y"+
"t.lepu.aenor.a"|"t.lepu.aenor.b"->"t.lepu.aenor.y"-
~("t.lepu.aenor.a"|"t.lepu.aenor.b")->"t.lepu.aenor.y"+
= "t.lepu._out" "t.lepu.aenor.a"
= "t.lepu._out" "t.lepu.buf2.a"
= "t.lepu._out" "t.lepu.buf1.y"
= "t.lepu.nor_out" "t.lepu.pull_up.a"
= "t.lepu.nor_out" "t.lepu.aenor.y"
"t.lepu.buf1.a"->"t.lepu.buf1._y"-
~("t.lepu.buf1.a")->"t.lepu.buf1._y"+
"t.lepu.buf1._y"->"t.lepu.buf1.y"-
~("t.lepu.buf1._y")->"t.lepu.buf1.y"+
= "t.lepu.reset_B" "t.lepu.aenor.b"
= "t.lepu.supply.vdd" "t.lepu.aenor.vdd"
= "t.lepu.supply.vdd" "t.lepu.buf2.vdd"
= "t.lepu.supply.vdd" "t.lepu.buf1.vdd"
= "t.lepu.supply.vss" "t.lepu.aenor.vss"
= "t.lepu.supply.vss" "t.lepu.buf2.vss"
= "t.lepu.supply.vss" "t.lepu.buf1.vss"
= "t.lepu.__out" "t.lepu.buf2.y"
"t.lepu.buf2.a"->"t.lepu.buf2._y"-
~("t.lepu.buf2.a")->"t.lepu.buf2._y"+
"t.lepu.buf2._y"->"t.lepu.buf2.y"-
~("t.lepu.buf2._y")->"t.lepu.buf2.y"+
= "t.lepu.in.d.d[0]" "t.lepu.in.r"
= "t.lepu.in.a" "t.lepu.buf1.a"
= "t.lepu.in.d.d[0]" "t.lepu.in.r"
= "t.lepu.out" "t.lepu.pull_up.y"
= "Vdd" "t.lepu.supply.vdd"
= "GND" "t.lepu.supply.vss"
= "t.out" "t.lepu.out"
= "t.in.d.d[0]" "t.in.r"
= "t.in.r" "t.lepu.in.r"
= "t.in.a" "t.lepu.in.a"
= "t.in.d.d[0]" "t.lepu.in.d.d[0]"
= "t.in.d.d[0]" "t.in.r"

48
test/unit_tests/line_end_pull_up/test.act Normal file
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/*************************************************************************
*
* This file is part of ACT dataflow neuro library.
* It's the testing facility for cell_lib_std.act
*
* Copyright (c) 2022 University of Groningen - Ole Richter
* Copyright (c) 2022 University of Groningen - Hugh Greatorex
* Copyright (c) 2022 University of Groningen - Michele Mastella
* Copyright (c) 2022 University of Groningen - Madison Cotteret
*
* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
*
* You may redistribute and modify this documentation and make products
* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
* for applicable conditions.
*
* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
*
* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
* these sources, You must maintain the Source Location visible in its
* documentation.
*
**************************************************************************
*/
import "../../dataflow_neuro/primitives.act";
import globals;
open tmpl::dataflow_neuro;
defproc lepu (a1of1 in; bool! out){
line_end_pull_up lepu(.in=in, .out=out);
//Low active Reset
bool _reset_B;
prs {
Reset => _reset_B-
}
lepu.supply.vss = GND;
lepu.supply.vdd = Vdd;
lepu.reset_B = _reset_B;
}
lepu t;

15
test/unit_tests/line_end_pull_up/test.prsim Normal file
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@ -0,0 +1,15 @@
watchall
set t.in.a 0
cycle
system "echo 'yo man'"
set Reset 0
cycle
set t.in.a 1
cycle
assert t.out 1