Added stuff for line end pull U/D
This commit is contained in:
17
test/unit_tests/line_end_pull_up/run/prsim.out
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17
test/unit_tests/line_end_pull_up/run/prsim.out
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t.in.a t.lepu.nor_out t.lepu.__out t.lepu.buf1._y t.lepu._out t.out t.lepu.buf2._y
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1 t.in.a : 0
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7093 t.lepu.buf1._y : 1 [by t.in.a:=0]
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17560 t.lepu._out : 0 [by t.lepu.buf1._y:=1]
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17562 t.lepu.nor_out : 1 [by t.lepu._out:=0]
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22313 t.lepu.buf2._y : 1 [by t.lepu._out:=0]
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23450 t.lepu.__out : 0 [by t.lepu.buf2._y:=1]
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yo man
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23450 Reset : 0
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23564 t._reset_B : 1 [by Reset:=0]
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88930 t.lepu.nor_out : 0 [by t._reset_B:=1]
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90656 t.out : 1 [by t.lepu.nor_out:=0]
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90656 t.in.a : 1
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90695 t.lepu.buf1._y : 0 [by t.in.a:=1]
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90710 t.lepu._out : 1 [by t.lepu.buf1._y:=0]
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91201 t.lepu.buf2._y : 0 [by t.lepu._out:=1]
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91214 t.lepu.__out : 1 [by t.lepu.buf2._y:=0]
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42
test/unit_tests/line_end_pull_up/run/test.prs
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42
test/unit_tests/line_end_pull_up/run/test.prs
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= "GND" "GND"
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= "Vdd" "Vdd"
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= "Reset" "Reset"
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"Reset"->"t._reset_B"-
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~("Reset")->"t._reset_B"+
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= "t._reset_B" "t.lepu.reset_B"
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~"t.lepu.pull_up.a"->"t.lepu.pull_up.y"+
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"t.lepu.aenor.a"|"t.lepu.aenor.b"->"t.lepu.aenor.y"-
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~("t.lepu.aenor.a"|"t.lepu.aenor.b")->"t.lepu.aenor.y"+
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= "t.lepu._out" "t.lepu.aenor.a"
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= "t.lepu._out" "t.lepu.buf2.a"
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= "t.lepu._out" "t.lepu.buf1.y"
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= "t.lepu.nor_out" "t.lepu.pull_up.a"
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= "t.lepu.nor_out" "t.lepu.aenor.y"
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"t.lepu.buf1.a"->"t.lepu.buf1._y"-
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~("t.lepu.buf1.a")->"t.lepu.buf1._y"+
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"t.lepu.buf1._y"->"t.lepu.buf1.y"-
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~("t.lepu.buf1._y")->"t.lepu.buf1.y"+
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= "t.lepu.reset_B" "t.lepu.aenor.b"
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= "t.lepu.supply.vdd" "t.lepu.aenor.vdd"
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= "t.lepu.supply.vdd" "t.lepu.buf2.vdd"
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= "t.lepu.supply.vdd" "t.lepu.buf1.vdd"
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= "t.lepu.supply.vss" "t.lepu.aenor.vss"
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= "t.lepu.supply.vss" "t.lepu.buf2.vss"
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= "t.lepu.supply.vss" "t.lepu.buf1.vss"
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= "t.lepu.__out" "t.lepu.buf2.y"
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"t.lepu.buf2.a"->"t.lepu.buf2._y"-
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~("t.lepu.buf2.a")->"t.lepu.buf2._y"+
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"t.lepu.buf2._y"->"t.lepu.buf2.y"-
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~("t.lepu.buf2._y")->"t.lepu.buf2.y"+
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= "t.lepu.in.d.d[0]" "t.lepu.in.r"
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= "t.lepu.in.a" "t.lepu.buf1.a"
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= "t.lepu.in.d.d[0]" "t.lepu.in.r"
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= "t.lepu.out" "t.lepu.pull_up.y"
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= "Vdd" "t.lepu.supply.vdd"
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= "GND" "t.lepu.supply.vss"
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= "t.out" "t.lepu.out"
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= "t.in.d.d[0]" "t.in.r"
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= "t.in.r" "t.lepu.in.r"
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= "t.in.a" "t.lepu.in.a"
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= "t.in.d.d[0]" "t.lepu.in.d.d[0]"
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= "t.in.d.d[0]" "t.in.r"
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48
test/unit_tests/line_end_pull_up/test.act
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48
test/unit_tests/line_end_pull_up/test.act
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/*************************************************************************
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*
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* This file is part of ACT dataflow neuro library.
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* It's the testing facility for cell_lib_std.act
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*
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* Copyright (c) 2022 University of Groningen - Ole Richter
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* Copyright (c) 2022 University of Groningen - Hugh Greatorex
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* Copyright (c) 2022 University of Groningen - Michele Mastella
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* Copyright (c) 2022 University of Groningen - Madison Cotteret
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*
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* This source describes Open Hardware and is licensed under the CERN-OHL-W v2 or later
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*
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* You may redistribute and modify this documentation and make products
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* using it under the terms of the CERN-OHL-W v2 (https:/cern.ch/cern-ohl).
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* This documentation is distributed WITHOUT ANY EXPRESS OR IMPLIED
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* WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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* AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN-OHL-W v2
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* for applicable conditions.
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*
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* Source location: https://git.web.rug.nl/bics/actlib_dataflow_neuro
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*
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* As per CERN-OHL-W v2 section 4.1, should You produce hardware based on
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* these sources, You must maintain the Source Location visible in its
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* documentation.
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*
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**************************************************************************
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*/
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import "../../dataflow_neuro/primitives.act";
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import globals;
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open tmpl::dataflow_neuro;
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defproc lepu (a1of1 in; bool! out){
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line_end_pull_up lepu(.in=in, .out=out);
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//Low active Reset
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bool _reset_B;
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prs {
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Reset => _reset_B-
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}
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lepu.supply.vss = GND;
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lepu.supply.vdd = Vdd;
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lepu.reset_B = _reset_B;
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}
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lepu t;
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15
test/unit_tests/line_end_pull_up/test.prsim
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15
test/unit_tests/line_end_pull_up/test.prsim
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watchall
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set t.in.a 0
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cycle
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system "echo 'yo man'"
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set Reset 0
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cycle
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set t.in.a 1
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cycle
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assert t.out 1
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