bics/actlib_dataflow_neuro
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cleaned up coders a bit

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alexmadison 2022-03-31 13:20:18 +02:00
parent 2e4cdd5029
commit 1d5d4738a2
1 changed files with 1 additions and 10 deletions
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dataflow_neuro/coders.act
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@ -116,17 +116,8 @@ defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
addr_buf.out.v = C2el.y;
// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
// ACK MAY HAVE BEEN DISCONNECTED HERE
// FOR TESTING PURPOSES
// !!!!!!!!!!!!!!!!
dly.out = addr_buf.out.a;
// ACK MAY HAVE BEEN DISCONNECTED HERE
// FOR TESTING PURPOSES
// !!!!!!!!!!!!!!!!
// Decoder X/Y And trees
decoder_dualrail<NxC,Nx> d_dr_x(.out = outx, .supply = supply);
@ -161,7 +152,7 @@ defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
* N_dly is a hard coded delay of the pull down circuit.
* It can be set to 0.
*/
export template<pint NxC, NyC, Nx, Ny, N_dly>
export template<pint NxC, NyC, Nx, Ny>
defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
// Buffer to recieve concat(x,y) address packet