vastly improved lazy synapse handshakes
This commit is contained in:
alexmadison
parent
cd5d41d7f8
commit
2e4cdd5029
@ -53,223 +53,186 @@ namespace tmpl {
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* Nc is the number of dualrail input channels.
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* Then builds N output AND gates, connecting to the right input wires.
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*/
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export template<pint Nc, N>
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defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
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// signal buffers
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sigbuf<N> in_tX[Nc];
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sigbuf<N> in_fX[Nc];
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(i:Nc:
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in_tX[i].supply = supply;
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in_tX[i].in = in.d[i].t;
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export template<pint Nc, N>
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defproc decoder_dualrail (Mx1of2<Nc> in; bool? out[N]; power supply) {
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// signal buffers
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sigbuf<N> in_tX[Nc];
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sigbuf<N> in_fX[Nc];
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(i:Nc:
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in_tX[i].supply = supply;
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in_tX[i].in = in.d[i].t;
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in_fX[i].supply = supply;
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in_fX[i].in = in.d[i].f;
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in_fX[i].supply = supply;
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in_fX[i].in = in.d[i].f;
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)
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// AND trees
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pint bitval;
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andtree<Nc> atree[N];
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(k:0..N-1:atree[k].supply = supply;)
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(i:0..N-1:
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(j:0..Nc-1:
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bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[i].in[j] = in_tX[j].out[i];
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// atree[i].in[j] = addr_buf.out.d.d[j].t;
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[]bitval = 0 ->
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atree[i].in[j] = in_fX[j].out[i];
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// atree[i].in[j] = addr_buf.out.d.d[j].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
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atree[i].out = out[i];
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)
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// AND trees
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pint bitval;
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andtree<Nc> atree[N];
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(k:0..N-1:atree[k].supply = supply;)
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(i:0..N-1:
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(j:0..Nc-1:
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bitval = (i & ( 1 << j )) >> j; // Get binary digit of integer i, column j
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[bitval = 1 ->
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atree[i].in[j] = in_tX[j].out[i];
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// atree[i].in[j] = addr_buf.out.d.d[j].t;
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[]bitval = 0 ->
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atree[i].in[j] = in_fX[j].out[i];
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// atree[i].in[j] = addr_buf.out.d.d[j].f;
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[]bitval >= 2 -> {false : "fuck"};
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]
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atree[i].out = out[i];
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)
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)
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}
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)
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}
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/**
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* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* Thus NxC should be something like NxC = ceil(log2(Nx))
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* but my guess is that we can't do logs...
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* N_dly_cfg is the number of config bits in the ACK delay line,
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
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dly_cfg[N_dly_cfg], reset_B; power supply) {
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/**
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* 2D decoder which uses a configurable delay from the VCtrees to buffer ack.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* Thus NxC should be something like NxC = ceil(log2(Nx))
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* but my guess is that we can't do logs...
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* N_dly_cfg is the number of config bits in the ACK delay line,
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* with all bits high corresponding to 2**N_dly_cfg -1 DLY4_X1 cells.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_dly (avMx1of2<NxC+NyC> in; bool? outx[Nx], outy[Ny],
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dly_cfg[N_dly_cfg], reset_B; power supply) {
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// Validity trees
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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// Validity trees
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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// Delay ack line. Ack line is delayed (but not the val)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
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addr_buf.out.v = C2el.y;
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// Delay ack line. Ack line is delayed (but not the val)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .vdd = supply.vdd, .vss = supply.vss);
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addr_buf.out.v = C2el.y;
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// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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dly.out = addr_buf.out.a;
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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// delayprog<N_dly_cfg> dly(.in = tielow.y, .s = dly_cfg, .supply = supply);
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delayprog<N_dly_cfg> dly(.in = C2el.y, .s = dly_cfg, .supply = supply);
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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dly.out = addr_buf.out.a;
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// ACK MAY HAVE BEEN DISCONNECTED HERE
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// FOR TESTING PURPOSES
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// !!!!!!!!!!!!!!!!
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// Decoder X/Y And trees
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decoder_dualrail<NxC,Nx> d_dr_x(.out = outx, .supply = supply);
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(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
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// Decoder X/Y And trees
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decoder_dualrail<NxC,Nx> d_dr_x(.out = outx, .supply = supply);
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(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
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decoder_dualrail<NyC,Ny> d_dr_y(.out = outy, .supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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decoder_dualrail<NyC,Ny> d_dr_y(.out = outy, .supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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}
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}
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export template<pint Nx, Ny>
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defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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AND2_X1 ands[Nx*Ny];
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(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
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(x:0..Nx-1:
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(y:0..Ny-1:
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ands[x + y*Nx].a = inx[x];
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ands[x + y*Nx].b = iny[y];
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ands[x + y*Nx].y = out[x + y*Nx];
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)
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)
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}
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/**
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* 2D decoder which uses synapse handshaking using line pulldowns.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* but my guess is that we can't do logs...
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* the req on a1of1 out is the req to each synapse.
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* The ack back from each line should go high when the synapse is charged.
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* N_dly is a hard coded delay of the pull down circuit.
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* It can be set to 0.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly>
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defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// Decoder X/Y And trees
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decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
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(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
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decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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// Validity
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
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.vdd = supply.vdd, .vss = supply.vss);
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// and grid for reqs into synapses
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and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
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(i:Nx*Ny: out[i].r = _and_grid.out[i];)
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// Acknowledge pull down time
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// Pull DOWNs on the reqB lines by synapses (easier to invert).
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bool _out_reqsB[Nx], _out_acksB[Nx]; // The vertical output ack lines from each syn.
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PULLDOWN2_X4 req_pulldowns[Nx*Ny];
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pint index;
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(i:Nx:
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(j:Ny:
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index = i + Nx*j;
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req_pulldowns[index].a = out[index].a;
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req_pulldowns[index].b = _out_acksB[i];
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req_pulldowns[index].y = _out_reqsB[i];
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req_pulldowns[index].vss = supply.vss;
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req_pulldowns[index].vdd = supply.vdd;
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)
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export template<pint Nx, Ny>
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defproc and_grid(bool! out[Nx*Ny]; bool? inx[Nx], iny[Ny]; power supply) {
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AND2_X1 ands[Nx*Ny];
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(i:0..Nx*Ny-1:ands[i].vss = supply.vss; ands[i].vdd = supply.vdd;)
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(x:0..Nx-1:
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(y:0..Ny-1:
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ands[x + y*Nx].a = inx[x];
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ands[x + y*Nx].b = iny[y];
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ands[x + y*Nx].y = out[x + y*Nx];
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)
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// ReqB keep cells
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KEEP_X1 req_keeps[Nx];
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(i:Nx:
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req_keeps[i].y = _out_reqsB[i];
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req_keeps[i].vdd = supply.vdd;
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req_keeps[i].vss = supply.vss;
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)
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// req-ack buffers
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// Delay needed here, since otherwise the pull up of reqB happens too quickly.
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// Means that the pull up may start fighting the synapse,
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// since the synapse has not yet retracted its ack.
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// Also there is the possibility, if really fast, that the line pull up block
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// doesn't yet see that the input is valid, and starts pulling up.
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// In any case, this delay is important.
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sigbuf<Ny> req_bufs[Nx];
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delay_chain<N_dly> ack_delays[Nx];
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(i:Nx:
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ack_delays[i].in = _out_reqsB[i];
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ack_delays[i].supply = supply;
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// req_bufs[i].in = _out_reqsB[i];
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req_bufs[i].in = ack_delays[i].out;
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req_bufs[i].out[0] = _out_acksB[i]; // DANGER DANGER
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req_bufs[i].supply = supply;
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)
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}
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/**
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* 2D decoder which uses synapse handshaking using line pulldowns.
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* Nx is the x size of the decoder array
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* NxC is the number of wires in the x channel.
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* but my guess is that we can't do logs...
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* the req on a1of1 out is the req to each synapse.
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* The ack back from each line should go high when the synapse is charged.
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* N_dly is a hard coded delay of the pull down circuit.
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* It can be set to 0.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly>
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defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; power supply) {
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)
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// Buffer to recieve concat(x,y) address packet
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buffer<NxC+NyC> addr_buf(.in = in, .reset_B = reset_B, .supply = supply);
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// Line end pull UPs (triggered once synapse reqs removed)
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OR2_X1 pu_ORs[Nx];
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PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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AND2_X1 pu_ANDs[Nx];
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(i:Nx:
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pu_ORs[i].a = _out_acksB[i];
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pu_ORs[i].b = d_dr_x.out[i];
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pu_ORs[i].vdd = supply.vdd;
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pu_ORs[i].vss = supply.vss;
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// Decoder X/Y And trees
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decoder_dualrail<NxC,Nx> d_dr_x(.supply = supply);
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(i:0..NxC-1:d_dr_x.in.d[i] = addr_buf.out.d.d[i];)
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decoder_dualrail<NyC,Ny> d_dr_y(.supply = supply);
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(i:0..NyC-1:d_dr_y.in.d[i] = addr_buf.out.d.d[i+NxC];)
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pu_ANDs[i].a = pu_ORs[i].y;
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pu_ANDs[i].b = reset_B; // TODO buffer
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pu_ANDs[i].vdd = supply.vdd;
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pu_ANDs[i].vss = supply.vss;
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// Validity
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vtree<NxC> vtree_x (.supply = supply);
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vtree<NyC> vtree_y (.supply = supply);
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(i:0..NxC-1:vtree_x.in.d[i].t = addr_buf.out.d.d[i].t;)
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(i:0..NxC-1:vtree_x.in.d[i].f = addr_buf.out.d.d[i].f;)
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(i:0..NyC-1:vtree_y.in.d[i].t = addr_buf.out.d.d[i+NxC].t;)
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(i:0..NyC-1:vtree_y.in.d[i].f = addr_buf.out.d.d[i+NxC].f;)
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A_2C_B_X1 C2el(.c1 = vtree_x.out, .c2 = vtree_y.out, .y = addr_buf.out.v,
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.vdd = supply.vdd, .vss = supply.vss);
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pu[i].a = pu_ANDs[i].y;
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pu[i].y = _out_reqsB[i];
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pu[i].vdd = supply.vdd;
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pu[i].vss = supply.vss;
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)
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// ORtree from all output reqs, back to the buffer ack.
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// This is instead of the ack that came from the delayed validity trees,
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// in decoder_2d_dly.
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ortree<Nx> _ortree(.out = addr_buf.out.a, .supply = supply);
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INV_X1 out_req_invs[Nx];
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(i:Nx:
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out_req_invs[i].a = _out_reqsB[i];
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out_req_invs[i].vdd = supply.vdd;
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out_req_invs[i].vss = supply.vss;
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// and grid for reqs into synapses
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and_grid<Nx, Ny> _and_grid(.inx = d_dr_x.out, .iny = d_dr_y.out, .supply = supply);
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(i:Nx*Ny: out[i].r = _and_grid.out[i];)
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_ortree.in[i] = out_req_invs[i].y;
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)
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}
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// Acknowledge pull down time
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// Pull DOWNs on the ackB lines by synapses (easier to invert).
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bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
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PULLDOWN2_X4 ack_pulldowns[Nx*Ny];
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pint index;
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(i:Nx:
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(j:Ny:
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index = i + Nx*j;
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ack_pulldowns[index].a = out[index].a;
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ack_pulldowns[index].b = d_dr_x.out[i];
|
||||
ack_pulldowns[index].y = _out_acksB[i];
|
||||
ack_pulldowns[index].vss = supply.vss;
|
||||
ack_pulldowns[index].vdd = supply.vdd;
|
||||
)
|
||||
)
|
||||
|
||||
// Line end pull UPs (triggered once reqs removed)
|
||||
PULLUP_X4 pu[Nx]; // TODO probably replace this with variable strength PU
|
||||
AND2_X1 pu_ANDs[Nx];
|
||||
(i:Nx:
|
||||
pu_ANDs[i].a = d_dr_x.out[i];
|
||||
pu_ANDs[i].b = reset_B; // TODO buffer
|
||||
pu_ANDs[i].vdd = supply.vdd;
|
||||
pu_ANDs[i].vss = supply.vss;
|
||||
|
||||
pu[i].a = pu_ANDs[i].y;
|
||||
pu[i].y = _out_acksB[i];
|
||||
pu[i].vdd = supply.vdd;
|
||||
pu[i].vss = supply.vss;
|
||||
)
|
||||
|
||||
// ORtree from all output acks, back to the buffer ack.
|
||||
// This is instead of the ack that came from the delayed validity trees,
|
||||
// in decoder_2d_dly.
|
||||
ortree<Nx> _ortree(.out = addr_buf.out.a, .supply = supply);
|
||||
INV_X1 out_ack_invs[Nx];
|
||||
(i:Nx:
|
||||
out_ack_invs[i].a = _out_acksB[i];
|
||||
out_ack_invs[i].vdd = supply.vdd;
|
||||
out_ack_invs[i].vss = supply.vss;
|
||||
|
||||
_ortree.in[i] = out_ack_invs[i].y;
|
||||
)
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user