disentangled synapse handshake circuits, passing tests
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alexmadison
parent
cd5900d4dc
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351b3ea151
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@ -93,7 +93,6 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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slice_data<N_IN-1, 0, NC_SYN> slice_pre_dec(.in = _demux.out1, .supply = supply);
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fifo<NC_SYN,N_BUFFERS> fifo_dmx2dec(.in = slice_pre_dec.out, .reset_B = _reset_BX, .supply = supply);
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decoder_2d_hybrid<NC_SYN_X, NC_SYN_Y, N_SYN_X, N_SYN_Y, N_SYN_DLY_CFG> decoder(.in = fifo_dmx2dec.out,
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.out = synapses,
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.hs_en = register.data[0].d[0].t, // Defaults to handshake disable
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.ack_disable = register.data[1].d[2].t, // Defaults to ack enabled
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.supply = supply, .reset_B = _reset_BX);
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@ -103,7 +102,16 @@ defproc texel_core (avMx1of2<N_IN> in, out;
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dly_cfg_inverters[i].vdd = supply.vdd;
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dly_cfg_inverters[i].vss = supply.vss;
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decoder.dly_cfg[i] = dly_cfg_inverters[i].y;
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) // This sexy hack means that the inverters are max delay throughout the register flush operations.
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)
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// Synapse handshake circuits, to be removed for innovus
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decoder_2d_synapse_hs<N_SYN_X, N_SYN_Y> _synapses(
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.synapses = synapses,
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.in_req_x = decoder.out_req_x, .in_req_y = decoder.out_req_y,
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.in_ackB_pullups = decoder.out_ackB_pullups,
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.out_req_x_pullups = decoder.in_req_x_pullups,
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.out_ackB_decoder = decoder.in_ackB_decoder,
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.supply = supply);
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// Neurons + encoder
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pint NC_NRN;
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@ -382,6 +382,45 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
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}
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/**
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* Synapse handshaking stuff which exists in the core, and so will not be spawned in
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* when innovusing all the periphery.
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*/
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export template<pint Nx, Ny>
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defproc decoder_2d_synapse_hs (bool? in_req_x[Nx], in_req_y[Ny]; a1of1 synapses[Nx*Ny];
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bool out_ackB_decoder[Nx];
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bool in_ackB_pullups[Nx];
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bool out_req_x_pullups[Nx];
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power supply) {
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// and grid for reqs into synapses
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and_grid<Nx, Ny> _and_grid(.inx = in_req_x, .iny = in_req_y, .supply = supply);
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(i:Nx*Ny: synapses[i].r = _and_grid.out[i];)
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// Pull DOWNs on the ackB lines by synapses (easier to invert).
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A_2N_U_X4 ack_pulldowns[Nx*Ny];
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pint index;
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(i:Nx:
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(j:Ny:
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index = i + Nx*j;
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ack_pulldowns[index].n1 = synapses[index].a;
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ack_pulldowns[index].n2 = in_req_x[i]; // GET REFRHRESED IN CORE
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ack_pulldowns[index].y = out_ackB_decoder[i];
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ack_pulldowns[index].vss = supply.vss;
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ack_pulldowns[index].vdd = supply.vdd;
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)
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)
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// Connect the ackB lines together
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(i:Nx: out_ackB_decoder[i] = in_ackB_pullups[i];)
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// Pipe req x lines down to the ackB pullups
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(i:Nx: out_req_x_pullups[i] = in_req_x[i];)
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}
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/**
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* 2D decoder which uses either synapse handshaking, or just a delay.
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* Controlled by the "hs_en" (handshake_enable) config bit.
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@ -395,8 +434,11 @@ defproc decoder_2d_hs (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? reset_B; po
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* Is needed in case there are instabilities while we fiddle with delays.
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*/
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export template<pint NxC, NyC, Nx, Ny, N_dly_cfg>
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defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable,
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reset_B; power supply) {
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defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; bool! out_req_x[Nx], out_req_y[Ny]; bool? dly_cfg[N_dly_cfg], hs_en, ack_disable;
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bool in_ackB_decoder[Nx]; // AckB lines back to the decoder for handshaking
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bool out_ackB_pullups[Nx]; // AckB lines from the line end pull ups
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bool in_req_x_pullups[Nx]; // req x lines going to the line pull ups
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bool? reset_B; power supply) {
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bool _reset_BX[Nx];
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sigbuf<Nx> reset_sb(.in = reset_B, .out = _reset_BX, .supply = supply);
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@ -416,13 +458,9 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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// sig buf for reqx lines, since they go to synapse pull down gates.
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// Signals to the and-grid are buffered therein.
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sigbuf_boolarray<Nx,15> d_dr_xX(.in = d_dr_x.out, .supply = supply);
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// sigbuf<15> d_dr_xX[Nx]; // GET REFRESHED IN CORE
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// (i:Nx:
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// d_dr_xX[i].in = d_dr_x.out[i];
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// d_dr_xX[i].supply = supply;
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// )
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d_dr_xX.out = out_req_x;
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sigbuf_boolarray<Ny,47> d_dr_yX(.in = d_dr_y.out, .supply = supply);
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d_dr_yX.out = out_req_y;
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// Validity
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@ -432,28 +470,7 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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.vdd = supply.vdd, .vss = supply.vss);
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// and grid for reqs into synapses
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and_grid<Nx, Ny> _and_grid(.inx = d_dr_xX.out, .iny = d_dr_yX.out, .supply = supply);
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(i:Nx*Ny: out[i].r = _and_grid.out[i];)
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// Acknowledge pull down time
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// Pull DOWNs on the ackB lines by synapses (easier to invert).
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bool _out_acksB[Nx]; // The vertical output ack lines from each syn.
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A_2N_U_X4 ack_pulldowns[Nx*Ny];
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pint index;
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(i:Nx:
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(j:Ny:
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index = i + Nx*j;
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ack_pulldowns[index].n1 = out[index].a;
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ack_pulldowns[index].n2 = d_dr_xX.out[i]; // GET REFRHRESED IN CORE
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ack_pulldowns[index].y = _out_acksB[i];
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ack_pulldowns[index].vss = supply.vss;
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ack_pulldowns[index].vdd = supply.vdd;
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)
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)
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// Line end pull UPs (triggered once reqs removed)
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// Use two pullups rather than and-pullup
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// bc smaller
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@ -462,14 +479,14 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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A_2P_U_X4 pu[Nx]; // TODO probably replace this with variable strength PU
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A_1P_U_X4 pu_reset[Nx];
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(i:Nx:
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pu[i].p1 = d_dr_xX.out[i];
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pu[i].p1 = in_req_x_pullups[i];
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pu[i].p2 = hs_enB;
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pu[i].y = _out_acksB[i];
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pu[i].y = out_ackB_pullups[i];
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pu[i].vdd = supply.vdd;
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pu[i].vss = supply.vss;
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pu_reset[i].p1 = _reset_BX[i];
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pu_reset[i].y = _out_acksB[i];
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pu_reset[i].y = out_ackB_pullups[i];
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pu_reset[i].vdd = supply.vdd;
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pu_reset[i].vss = supply.vss;
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)
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@ -479,16 +496,17 @@ defproc decoder_2d_hybrid (avMx1of2<NxC+NyC> in; a1of1 out[Nx*Ny]; bool? dly_cfg
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(i:Nx:
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keeps[i].vdd = supply.vdd;
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keeps[i].vss = supply.vss;
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keeps[i].y = _out_acksB[i];
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keeps[i].y = out_ackB_pullups[i];
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)
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// ORtree from all output acks, back to the buffer ack.
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// This is instead of the ack that came from the delayed validity trees,
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// in decoder_2d_dly.
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ortree<Nx> _ortree(.supply = supply);
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INV_X1 out_ack_invs[Nx];
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(i:Nx:
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out_ack_invs[i].a = _out_acksB[i];
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out_ack_invs[i].a = in_ackB_decoder[i];
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out_ack_invs[i].vdd = supply.vdd;
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out_ack_invs[i].vss = supply.vss;
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